C8051F380 데이터 시트보기 (PDF) - Silicon Laboratories

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C8051F380

Full Speed USB Flash MCU Family

Silicon Laboratories 

C8051F380/1/2/3/4/5/6/7/C

Figure 14.9. Multiplexed 8-bit MOVX without Bank Select Timing ........................ 108

Figure 14.10. Multiplexed 8-bit MOVX with Bank Select Timing ........................... 109

Figure 17.1. Reset Sources ................................................................................... 129

Figure 17.2. Power-On and VDD Monitor Reset Timing ....................................... 130

Figure 18.1. Flash Program Memory Map and Security Byte ................................ 137

Figure 19.1. Oscillator Options .............................................................................. 142

Figure 19.2. External Crystal Example .................................................................. 150

Figure 20.1. Port I/O Functional Block Diagram (Port 0 through Port 3) ............... 153

Figure 20.2. Port I/O Cell Block Diagram .............................................................. 154

Figure 20.3. Peripheral Availability on Port I/O Pins .............................................. 155

Figure 20.4. Crossbar Priority Decoder in Example Configuration

(No Pins Skipped) ............................................................................................ 156

Figure 20.5. Crossbar Priority Decoder in Example Configuration (3 Pins Skipped)

............................................................................................................. 157

Figure 21.1. USB0 Block Diagram ......................................................................... 172

Figure 21.2. USB0 Register Access Scheme ........................................................ 175

Figure 21.3. USB FIFO Allocation ......................................................................... 181

Figure 22.1. SMBus Block Diagram ...................................................................... 205

Figure 22.2. Typical SMBus Configuration ............................................................ 206

Figure 22.3. SMBus Transaction ........................................................................... 207

Figure 22.4. Typical SMBus SCL Generation ........................................................ 209

Figure 22.5. Typical Master Write Sequence ........................................................ 223

Figure 22.6. Typical Master Read Sequence ........................................................ 224

Figure 22.7. Typical Slave Write Sequence .......................................................... 225

Figure 22.8. Typical Slave Read Sequence .......................................................... 226

Figure 23.1. UART0 Block Diagram ...................................................................... 232

Figure 23.2. UART0 Baud Rate Logic ................................................................... 233

Figure 23.3. UART Interconnect Diagram ............................................................. 234

Figure 23.4. 8-Bit UART Timing Diagram .............................................................. 234

Figure 23.5. 9-Bit UART Timing Diagram .............................................................. 235

Figure 23.6. UART Multi-Processor Mode Interconnect Diagram ......................... 236

Figure 24.1. UART1 Block Diagram ...................................................................... 240

Figure 24.2. UART1 Timing Without Parity or Extra Bit ......................................... 242

Figure 24.3. UART1 Timing With Parity ................................................................ 242

Figure 24.4. UART1 Timing With Extra Bit ............................................................ 242

Figure 24.5. Typical UART Interconnect Diagram ................................................. 243

Figure 24.6. UART Multi-Processor Mode Interconnect Diagram ......................... 244

Figure 25.1. SPI Block Diagram ............................................................................ 250

Figure 25.2. Multiple-Master Mode Connection Diagram ...................................... 252

Figure 25.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram

............................................................................................................. 252

Figure 25.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram

............................................................................................................. 253

Figure 25.5. Master Mode Data/Clock Timing ....................................................... 255

Figure 25.6. Slave Mode Data/Clock Timing (CKPHA = 0) ................................... 255

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