CA5130 데이터 시트보기 (PDF) - Intersil
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CA5130 Datasheet PDF : 19 Pages
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CA5130, CA5130A
Schematic Diagram
BIAS CIRCUIT
CURRENT SOURCE FOR
Q6 AND Q7
Q1
D1
Z1
D2
8.3V
D3
R1
D4
40kΩ R2
5kΩ
NON-INV.
INPUT
3+
INV. INPUT
2-
Q2
Q4
INPUT
STAGE
D5 D6 (NOTE 6) D7 D8
Q6
Q7
R3
R4
1kΩ
1kΩ
Q9 Q10
“CURRENT SOURCE
LOAD” FOR Q11
Q3
Q5
SECOND
STAGE
Q11
OUTPUT
STAGE
R5
R6
1kΩ
1kΩ
7 V+
Q8
OUTPUT
6
Q12
5
OFFSET NULL
1
COMPENSATION
NOTE:
6. Diodes D5 through D8 provide gate oxide protection for MOSFET Input Stage.
Block Diagram
8
STROBING
4 V-
CA5130
200µA 1.35mA
BIAS CKT.
200µA
V+
7
8mA (NOTE 7)
0mA (NOTE 8)
+
3
INPUT
2
-
AV ≈ 5X
AV ≈
6000X
AV ≈
30X
51
CC
8
OFFSET
NULL
COMPENSATION
(WHEN REQUIRED)
STROBE
OUTPUT
6
V-
4
NOTES:
7. Total supply voltage (for indicated voltage gains)
= 15V with input terminals biased so that
Terminal 6 potential is +7.5V above Terminal 4.
8. Total supply voltage (for indicated voltage gains)
= 15V with output terminal driven to either
supply rail.
5
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