CAT24C208 데이터 시트보기 (PDF) - Catalyst Semiconductor => Onsemi
부품명
상세내역
제조사
CAT24C208 Datasheet PDF : 13 Pages
| |||
CAT24C208
ARBITRATION
The device performs a simplistic arbitration between the
DDC and DSP ports. While the arbitration scheme
described is not foolproof, it does prevent most errors.
Arbitration logic within the device monitors activity on
DDC_SCL and DSP_SCL. When both I2C ports are idle,
DDC_SCL and DSP_SCL are both high and the
arbitration logic is inactive. When a START condition is
detected on either port, the opposite port SCL line is
pulled low, holding off activity on that port. When the
initiating SCL line has remained high for one full second,
the arbitration logic assumes that the initiating devices is
finished and releases the other SCL line. If the non-
initiating device has been waiting for access, it can now
read or write the device.
CONFIGURATION REGISTER
MSB
LSB
Register Function
Configuration Register
7
6
5
4
3
2
1
0
X
X
X
X WE AB1 AB0 NB
Function Description:
NB:
Number of memory banks in DDC port memory map. 0 = 2 Banks, 1 = 1 Bank
AB0:
Active Bank Control Bit 0 (See Figure 19)
AB1:
Active Bank Control Bit 1 (See Figure 19)
WE DDC:
Write Enable 0 = Write Disabled, 1= Write Enabled
Note: WE affects only write operations from the DDC port, not the display port. The display port always has write access.
Figure 19. Configuration Register Truth Table
AB1
AB0
NB
0
X
0
0
X
0
1
0
0
1
1
0
X
X
1
EDID
Select Pin
0
1
X
X
X
The configuration register is a non-volatile register and
is available from either DSP or DDC port at address 62h/
63h for write and read resp.
Figure 20. Read Configuration Register
START
0110 0011 ACK
DATA
NO ACK STOP
Active Bank
Lower Bank
Upper Bank
Lower Bank
Upper Bank
Lower (only) Bank
Figure 21. Write Configuration Register
START 0110 0010 ACK DUMMY ADDRESS ACK XXXX WE AB1 AB0 NB ACK STOP
Doc. No. 1044, Rev. F
10
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Share Link: 