CAT24C21LE-TE13 데이터 시트보기 (PDF) - Catalyst Semiconductor => Onsemi

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CAT24C21LE-TE13

1-kb Dual Mode Serial EEPROM for VESA™ "Plug-and-Play"

Catalyst Semiconductor => Onsemi 

CAT24C21

PIN DESCRIPTION

The SCL serial clock input pin is used to clock all data

transfers into or out of the device when in the

bi-directional mode.

The SDA bi-directional serial data/address pin is used to

transfer data into and out of the device. The SDA pin is

an open drain output and can be wire-ORed with other

open drain or open collector outputs.

FUNCTIONAL DESCRIPTION

The CAT24C21 has two modes of operation: the transmit-

only mode and the bi-directional mode. There is a

separate 2-wire protocol to support each mode, each

having a separate clock input (VCLK and SCL

respectively) and both modes sharing a common bi-

directional data line (SDA). The CAT24C21 enters the

transmit-only mode upon power up and begins outputting

data on the SDA pin with each clock signal on the VCLK

pin. The device will remain in the transmit-only mode

until there is a valid HIGH to LOW transition on the SCL

pin, when it will switch to the bi-directional mode (Figure

1). Once in the bi-directinal mode, the only way to return

to the transmit-only mode is by powering down the

device.

The VCLK serial clock input pin is used to clock data out

of the device when in transmit-only mode. When held

low, in bi-directional mode, it will inhibit write operations.

TRANSMIT-ONLY MODE: (DDC1)

Upon power-up, the CAT24C21 will output valid data

only after it has been initialized. During initialization,

data will not be available until after the first nine clocks

are sent to the device (Figure 2). The starting address for

the transmit-only mode can be determined during

initialization. If the SDA pin is high during the first eight

clocks, the starting address will be 7FH. If the SDA pin

is low during the first eight clocks, the starting address

will be 00H. During the ninth clock, SDA will be in the high

impedance state.

Data is transmitted in 8 bit words with the most significant

bit first, followed by a 9th 'don't care' bit which will be in

the high impedance state (Figure 3). The CAT24C21 will

continuously sequence through the entire memory array

as long as VCLK is present and no falling edges on SCL

are detected. When the maximum address (7FH) is

reached, addressing will wrap around to the zero location

(00H) and transmitting will continue. The bi-directional

mode clock (SCL) pin must be held high for the device

to remain in the transmit-only mode.

Figure 1. Mode Transition

SCL

SDA

Transmit-Only Mode Bi-Directional Mode

TVHZ

VCLK

Figure 2. Device Initialization for Transmit-only Mode

SCL

SDA

VCLK

Doc. No. 1032, Rev. O

SDA at high impedance for 9 clock cycles

Bit8 Bit7 Bit6 Bit5 Bit4

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

TVPU

TVAA

4

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