CAT25010 데이터 시트보기 (PDF) - Catalyst Semiconductor => Onsemi

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CAT25010

1-Kb, 2-Kb and 4-Kb SPI Serial CMOS EEPROM

Catalyst Semiconductor => Onsemi 

CAT25010, CAT25020, CAT25040

Hold Operation

The ¯H¯O¯L¯D¯ input can be used to pause communication

between host and CAT25010/20/40. To pause, ¯H¯O¯L¯D¯

must be taken low while SCK is low (Figure 10).

During the hold condition the device must remain

selected (C¯¯S low). During the pause, the data output

pin (SO) is tri-stated (high impedance) and SI

transitions are ignored. To resume communication,

H¯¯O¯L¯D¯ must be taken high while SCK is low.

DESIGN CONSIDERATIONS

The CAT25010/20/40 devices incorporate Power-On

Reset (POR) circuitry which protects the internal logic

against powering up in the wrong state. The device

will power up into Standby mode after VCC exceeds

the POR trigger level and will power down into Reset

mode when VCC drops below the POR trigger level.

This bi-directional POR behavior protects the device

against ‘brown-out’ failure following a temporary loss

of power.

The CAT25010/20/40 device powers up in a write

disable state and in a low power standby mode. A

WREN instruction must be issued prior any writes to

the device.

After power up, the C¯¯S pin must be brought low to

enter a ready state and receive an instruction. After a

successful byte/page write or status register write, the

device goes into a write disable mode. The C¯¯S input

must be set high after the proper number of clock

cycles to start the internal write cycle. Access to the

memory array during an internal write cycle is ignored

and programming is continued. Any invalid op-code

will be ignored and the serial output pin (SO) will

remain in the high impedance state.

Figure 10. H¯¯O¯L¯D¯ Timing

CS

SCK

HOLD

SO

tCD

tHD

tHZ

Note: Dashed Line = mode (1, 1) - - - - - -

tCD

tHD

HIGH IMPEDANCE

tLZ

Doc. No. MD-1006 Rev. T

10

© Catalyst Semiconductor, Inc.

Characteristics subject to change without notice

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