CAT93C56VIT3 데이터 시트보기 (PDF) - ON Semiconductor
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CAT93C56VIT3 Datasheet PDF : 17 Pages
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CAT93C56, CAT93C57
Erase All
Upon receiving an ERAL command (Figure 7), the CS
(Chip Select) pin must be deselected for a minimum of
tCSMIN. The falling edge of CS will start the self clocking
clear cycle of all memory locations in the device. The
clocking of the SK pin is not necessary after the device has
entered the self clocking mode. The ready/busy status of the
CAT93C56/57 can be determined by selecting the device
and polling the DO pin. Once cleared, the contents of all
memory bits return to a logical “1” state.
Write All
Upon receiving a WRAL command and data, the CS
(Chip Select) pin must be deselected for a minimum of
tCSMIN (Figure 8). The falling edge of CS will start the self
clocking data write to all memory locations in the device.
The clocking of the SK pin is not necessary after the device
has entered the self clocking mode. The ready/busy status of
the CAT93C56/57 can be determined by selecting the device
and polling the DO pin. It is not necessary for all memory
locations to be cleared before the WRAL command is
executed.
SK
CS
STATUS VERIFY
STANDBY
tCS
DI
1
00
10
HIGH−Z
DO
tSV
BUSY READY
tEW
tHZ
HIGH−Z
Figure 7. ERAL Instruction Timing
SK
CS
STATUS VERIFY STANDBY
tCSMIN
DI
1
000
1
DN
D0
tSV
tHZ
DO
BUSY READY
HIGH−Z
tEW
Figure 8. WRAL Instruction Timing
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