CS42L51(2005) 데이터 시트보기 (PDF) - Cirrus Logic

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CS42L51
(Rev.:2005)

Low Power, Stereo CODEC with Headphone Amp

Cirrus Logic 

CS42L51

LIST OF FIGURES

Figure 1. Typical Connection Diagram (Software Mode) .......................................................................... 10

Figure 2. Typical Connection Diagram (Hardware Mode)......................................................................... 11

Figure 3. Headphone Output Test Load.................................................................................................... 19

Figure 4. Serial Audio Interface Slave Mode Timing................................................................................. 21

Figure 5. TDM Serial Audio Interface Timing ............................................................................................ 21

Figure 6. Serial Audio Interface Master Mode Timing............................................................................... 21

Figure 7. Control Port Timing - I²C ............................................................................................................ 22

Figure 8. Control Port Timing - SPI Format............................................................................................... 23

Figure 9. Analog Input Architecture........................................................................................................... 28

Figure 10. MIC Input Mix w/Common Mode Rejection.............................................................................. 30

Figure 11. Differential Input....................................................................................................................... 30

Figure 12. ALC .......................................................................................................................................... 31

Figure 13. Noise Gate Attenuation............................................................................................................ 32

Figure 14. Output Architecture .................................................................................................................. 33

Figure 15. De-Emphasis Curve................................................................................................................. 33

Figure 16. Beep Configuration Options..................................................................................................... 34

Figure 17. Peak Detect & Limiter .............................................................................................................. 35

Figure 18. Master Mode Timing ................................................................................................................ 38

Figure 19. Tri-State Serial Port ................................................................................................................. 38

Figure 20. I²S Format ................................................................................................................................ 39

Figure 21. Left-Justified Format ................................................................................................................ 39

Figure 22. Right-Justified Format (DAC only) ........................................................................................... 39

Figure 23. Initialization Flow Chart............................................................................................................ 41

Figure 24. Control Port Timing in SPI Mode ............................................................................................. 42

Figure 25. Control Port Timing, I²C Write.................................................................................................. 43

Figure 26. Control Port Timing, I²C Read.................................................................................................. 43

Figure 27. AIN & PGA Selection ............................................................................................................... 53

Figure 28. THD+N vs. Ouput Power per Channel at 1.8 V (16 Ω load) .................................................... 72

Figure 29. THD+N vs. Ouput Power per Channel at 2.5 V (16 Ω load) .................................................... 72

Figure 30. THD+N vs. Ouput Power per Channel at 1.8 V (32 Ω load) .................................................... 73

Figure 31. THD+N vs. Ouput Power per Channel at 2.5 V (32 Ω load) .................................................... 73

Figure 32. ADC THD+N vs. Frequency w/Capacitor Effects..................................................................... 74

Figure 33. ADC Passband Ripple ............................................................................................................. 78

Figure 34. ADC Stopband Rejection ......................................................................................................... 78

Figure 35. DAC Passband Ripple ............................................................................................................. 78

Figure 36. DAC Stopband ......................................................................................................................... 78

Figure 35. DAC Transition Band ............................................................................................................... 78

Figure 36. DAC Transition Band (Detail)................................................................................................... 78

Figure 35. ADC Transition Band ............................................................................................................... 78

Figure 36. ADC Transition Band (Detail)................................................................................................... 78

6

DS679A2

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