CDP1802AC/3 데이터 시트보기 (PDF) - Intersil
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CDP1802AC/3 Datasheet PDF : 27 Pages
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CDP1802AC/3
CPU Block Diagram
I/O REQUESTS
MEMORY ADDRESS LINES I/O FLAGS
MA6 MA4 MA2 MA0 EF1 EF3
MA7 MA5 MA3 MA1
EF2 EF4
DMA
OUT
DMA
IN INT
CONTROL
CLEAR
WAIT
MUX
A
CLOCK
LOGIC
CONTROL AND
TIMING LOGIC
TO INSTRUCTION
DECODE
CLOCK
XTAL
SCO
SCI
STATE
CODES
Q LOGIC
TPA
TPB
MWR
SYSTEM
TIMING
MRD
B
ALU
R(0).1
R(0).0
REGISTER
ARRAY
R(1).1 R(1).0 R
DF
INCR/
DECR
R(2).1 R(2).0
N0
D
R(9).1 R(9).0
LATCH
AND
X
T
P
R(A).1 R(A).0
DECODE
I
N
N1
I/O
COMMANDS
N2
R(E).1 R(E).0
R(F).1 R(F).0
BUS 0
8-BIT BIDIRECTIONAL DATA BUS
BUS 1
BUS 2
BUS 3
BUS 4
BUS 5
BUS 6
BUS 7
FN1441 Rev 3.00
October 17, 2008
Page 3 of 27
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