CDP68HC68P1 데이터 시트보기 (PDF) - Intersil
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CDP68HC68P1 Datasheet PDF : 9 Pages
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MOSI
CE
SCK
ID1
ID0
CDP68HC68P1
SHIFT REGISTER
CONTROL
LOGIC
MISO
DIRECTION
REGISTER
COMPARATOR
INPUT/OUTPUT
DIRECTION
REGISTER
D0 - D7
FIGURE 1. SINGLE PORT I/O BLOCK DIAGRAM
CHIP
ENABLE
DATA IN
DATA OUT
CLOCK
CE
CDP68HC68P1
MOSI
D0 - D7
MISO
SCK
ID0
ID1
I/O PORT
DATA
IN/OUT
CHIP
IDENTIFY
FIGURE 2. SINGLE PORT I/O
Pin Descriptions
ID0, ID1 - Chip identify pins, normally tied to VDD to VSS.
The 4 possible combinations of these pins allow 4 I/Os to
share a common chip enable. When the levels at these pins
match those of the identify bits in the control word, the serial
bus is enabled. The chip identify pins will retain their
previous logic state if the lines driving them become Hi-Z.
MISO - Master-in, Slave out pin. Data bytes are shifted out
at this pin most significant bit first. When the chip enable
signal is high, this pin is Hi-Z.
MOSI - Master-out, Slave in pin. Data bytes are shifted in at
this pin most significant bit first. This pin will retain its
previous logic state if its driving line becomes Hi-Z.
SCK - Serial clock input. This input causes serial data to be
latched from the MOSI input and shifted out on the MISO
output.
CE - A negative chip enable input. A high to low transition on
this pin latches the inactive SCK polarity and compare flag
and indicates the start of a data transfer. The serial interface
logic is enabled only when CE is low. This pin will retain its
previous logic state if its driving line becomes Hi-Z.
D0 -D7 - I/O Port pins. Individual programmable inputs or
outputs.
VDD and VSS - Positive and negative power supply line.
All pins except the power supply lines and MISO have
Schmitt-trigger buffered inputs.
2
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