CDP68HC68P1M 데이터 시트보기 (PDF) - Intersil

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CDP68HC68P1M

CMOS Serial 8-Bit Input/Output Port

Intersil 

CDP68HC68P1

Absolute Maximum Ratings

DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . . . -0.5V to +7V

(Voltage Referenced to VSS Terminal)

Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V

DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . . ±10mA

Power Dissipation Per Package (PD)

TA

TA

=

=

-40oC to 60oC (Package Type E)

60oC to 85oC (Package Type E)

Derate Linearly at . . . . . . . . . . . . . . . . .

.

.

.

.

.

.

.

.

. . . . . . . . . . .500mW

12mW/oC to 200mW

TA = -40oC to 60oC (Package Type M) (Note 1) . . . . . . . .300mW

TA = 60oC to 85oC

Derate Linearly at .

(Package

........

Type

.....

M)

..

(Note

.....

1)

. 5mW/oC

to

175mW

Thermal Information

Thermal Resistance (Typical, Note 2)

θJA (oC/W) θJC (oC/W)

PDIP Package . . . . . . . . . . . . . . . . . . .

90

NA

SOIC Package . . . . . . . . . . . . . . . . . . . 110

NA

Device Dissipation Per Output Transistor . . . . . . . . . . . . . . .100mW

MaTxAim=uFmulSl PtoarackgaegTeeTmepmepraetruarteurReaRnagneg(eTS(ATlGl P) a. c.k.a-g6e5ToCypteos1) 50oC

Maximum Lead Temperature (Soldering 10s)

At Distance 1/16in ± 1/32in. (1.59 ± 0.79mm) . . . . . . . . . . .265oC

(SOIC - Lead Tips Only)

Operating Conditions

Temperature Range (TA)

Package Type E, M . . .

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

-55oC

to

85oC

DC Operating Voltage Range . . . . . . . . . . . . . . . . . 3V Min, 6V Max

Serial Clock Frequency, fSCK, VDD = 3V. . . . . . . . . . . 1.05MHz Max

Serial Clock Frequency, fSCK, VDD = 4.5V . . . . . . . . . . 2.1MHz Max

Input Voltage Range, VIH . . . . . . . . . . . . . . . . . . . . VDD +0.3V Max

Input Voltage Range, VIL . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V Min

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. Printed circuit board mount: 57mm x 57mm minimum area x 1.6mm thick G10 epoxy glass, or equivalent.

2. θJA is measured with the component mounted on an evaluation PC board in free air.

Static Electrical Specifications TA = -40oC to 85oC, VDD = 3.3V ±10%, Unless Otherwise Specified.

PARAMETER

SYMBOL

TEST

CONDITIONS

(NOTE 3)

MIN

TYP

Output Voltage

Input Voltage

D0 - D7

Positive Trigger Threshold

VOH

VOL

IOH = -0.4mA, VDD = 3V

IOL = 0.4mA, VDD = 3V

VP

2.7

-

-

-

1.85

-

Negative Trigger Threshold

VN

Hysteresis

VIH

Input Voltage

ID0, ID1, MOSI, SCK, CE

VP

Positive Trigger Threshold

0.85

-

0.85

-

1.3

-

Negative Trigger Threshold

VN

0.8

-

Hysteresis

VIH

0.5

-

Input Leakage Current

IIN

-

-

Standby Device Current

IDDS

-

1

Three-State Output Leakage Current

IOUT

-

-

Operating Device Current (Note 4)

IOPER VIN = VIL, VIH

-

0.1

Input Capacitance

CIN

VIN = 0V, f = 1MHz, TA = 25oC

-

4

NOTES:

3. Typical values are for TA = 25oC and nominal VDD.

4. Outputs open circuited; cycle time = Min. tCYCLE, duty = 100%.

MAX

-

0.3

2.4

1.35

1.25

1.9

1.2

0.95

±1

15

±10

1

6

UNITS

V

V

V

V

V

V

V

V

µA

µA

µA

mA

pF

3

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