CDP68HC68P1E 데이터 시트보기 (PDF) - Intersil
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CDP68HC68P1E Datasheet PDF : 9 Pages
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CDP68HC68P1
Static Electrical Specifications At TA = -40oC to 85oC, VDD = 5V ±10%, Unless Otherwise Specified.
PARAMETER
SYMBOL
TEST
CONDITIONS
(NOTE 5)
MIN
TYP
Output Voltage
Input Voltage
D0 - D7
Positive Trigger Threshold
VOH
VOL
VOH
VOL
IOH = -1.6mA, VDD = 4.5V
IOL = 1.6mA, VDD = 4.5V
IOH ≤ 20µA, VDD = 4.5V
IOL ≤ 20µA, VDD = 4.5V
VP
3.7
-
-
-
4.4
-
-
-
2.15
-
Negative Trigger Threshold
VN
Hysteresis
VIH
Input Voltage
ID0, ID1, MOSI, SCK, CE
VP
Positive Trigger Threshold
1.35
-
0.8
-
3.15
-
Negative Trigger Threshold
VN
1.7
-
Hysteresis
VIH
1.3
-
Input Leakage Current
IIN
-
-
Standby Device Current
IDDS
-
1
Three-State Output Leakage Current
IOUT
-
-
Operating Device Current
(Note 6)
IOPER VIN = VIL, VIH
-
0.2
Input Capacitance
CIN
VIN = 0V, f = 1MHz, TA = 25oC
-
4
NOTES:
5. Typical values are for TA = 25oC and nominal VDD.
6. Outputs open circuited; cycle time = Min, tCYCLE, duty = 100%.
MAX
-
0.4
-
0.1
3.05
2
1.2
3.85
2.25
1.7
±1
15
±10
2
6
Dynamic Electrical Specifications - Bus Timing
VDD ±10%, VSS = 0V DC, TA = -40oC to 85oC, CL = 200pF.
See Figures 8 and 9.
PARAMETER
SYMBOL
VDD = 3.3V
MIN
MAX
VDD = 5V
MIN
MAX
Chip Enable Set-Up Time
Chip Enable after Clock Hold Time
Clock Width High
Clock Width Low
Data In to Clock Set-Up Time
Data In after Clock Hold Time
Clock to Data Propagation Delay
Chip Disable to Output High Z
Output Rise Time
Output Fall Time
Clock to Data Out Archive
Clock Recovery Time
tEVCV
200
-
100
-
tCVEX
250
-
125
-
tWH
400
-
200
-
tWL
400
-
200
-
tDVCV
200
-
100
-
tCVDX
200
-
100
-
tCVDV
-
200
-
100
tEXQZ
-
200
-
100
tr
-
200
-
100
tf
-
200
-
100
tCVQX
-
200
-
100
tREC
200
-
200
-
UNITS
V
V
V
V
V
V
V
V
V
V
µA
µA
µA
mA
pF
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
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