CDP68HC68P1 데이터 시트보기 (PDF) - Intersil
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CDP68HC68P1 Datasheet PDF : 9 Pages
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Waveforms
MISO
HI Z
CDP68HC68P1
C07
C06
COMPARE FLAG
D7
MOSI
X
CE
SCK
C07
C06
C05
C04
C00
D7
tDVCV
tDVCV
tCVDX
tWL
tEVCV
tWH
tREC
FIGURE 3. PORT-PIN DATA CHANGES
D6
D0
tr, tf
D6
D0
tCVDX
HI Z
X
tCVEX
MOSI
X
C07
C06
C05
C04
C00
X
MISO
CE
SCK
HI Z
tWL
tEVCV
C07
C06
COMPARE FLAG
D7
D6
D0
HI Z
tCVQX
tEXQZ
tCVDV
tWH
tREC
tCVEX
FIGURE 4. READ CYCLE TIMING WAVEFORMS
CE
SCK
(CPOL = 1)
CE
SHIFT INTERNAL
STROBE
SHIFT INTERNAL
STROBE
SCK
(CPOL = 0)
MOSI
OR
MISO
MSB MSB - 1
NOTE: CPOL and CPHA are bits in the CDP68HC05C4B and
CDP68HC05C16B MCU control register and determine inactive
clock polarity and phase. CPHA must always equal 1.
FIGURE 5. DATA TRANSFERS UTILIZING CLOCK INPUT
Introduction
The single port I/O is serially accessed via the synchronous
SPI bus. It features 8 data pins that are programmed as
inputs or outputs. Serial access consists of a two-byte
operation. The first byte shifted in is the control byte that
configures the device. The second byte transferred is the
data byte that is read from or written to the data register or
data direction register. This data byte can also be
programmed to act as a mask to set or clear individual bits.
Functional Description
The single port I/O consists of three byte-wide registers,
(data direction, data and shift) an input/output buffer and
control logic circuitry (See Figure 1). Data is transferred
between the I/O data and data direction registers via the shift
register. Once the I/O port is selected, the first byte shifted in
to the shift register is the control byte that selects the register
(the Data or Data direction register), determines data
transfer direction (read or write) and sets the compare
5
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