CF5018 데이터 시트보기 (PDF) - Nippon Precision Circuits
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CF5018 Datasheet PDF : 8 Pages
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PAD LAYOUT
(Unit: µm)
CF5018 series
VDD
NPC
Y
INHN
(720,730)
Q
VSS
(0,0) XT XTN
X
Chip size: 0.72 × 0.73mm
Chip thickness: 220 ± 30µm
PAD size: 90µm
Chip base: VDD level
PIN DESCRIPTION and PAD DIMENSIONS
Name
INHN
XT
XTN
VSS
Q
VDD
I/O
Description
I
Output state control input. High impedance when LOW (oscillator stops).
Power-saving pull-up resistor built-in.
I
Amplifier input
O
Amplifier output
Crystal connection pins.
Crystal is connected between XT and XTN.
–
Ground
O
Output. Output frequency. High impedance in standby mode
–
Supply voltage
BLOCK DIAGRAM
VDD VSS
XTN
CG
Rf1 Cf
CD
XT
Rf2
Pad dimensions [µm]
X
Y
151
277
238
131
503
131
588
345
588
598
131
598
Q
INHN
INHN = LOW active
SEIKO NPC CORPORATION —2
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