CL-PS6700-VC-A 데이터 시트보기 (PDF) - Cirrus Logic

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CL-PS6700-VC-A

Low-Power PC Card Controller for the CL-PS7111

Cirrus Logic 

CL-PS6700

Low-Power PC Card Controller

2.2.3 Additional Control for I/O Signals

Signal

Type

Power

Source

Description

PCM_IORD_L O

PCM_IOWR_L

pcm Single-mode.

Dual-mode.

Memory Mode: These signals remain deasserted.

I/O Mode: These signals are asserted during read (PCM_IORD_L) and write transfer

(PCM_IOWR_L) to the card I/O space or DMA devices. A PC Card does not respond to these

signals unless it is configured for I/O by the system.

2.2.4 Card Detect and Battery Status Signals

Signal

Type

Power

Source

Description

PCM_CD_L[2:1] I

PCM_BVD[2:1] I

VDDhi 00 – Card inserted

01 – Card partially inserted

10 – Card partially inserted

11 – Card not inserted

Single-mode. These pins indicate whether a card has been inserted into a socket. They are

positioned at opposite ends of the connector to ensure valid detection of card insertion; a

properly inserted card pulls both lines low. They are pulled up to VDDhi within the

CL-PS6700 until a card is inserted (which pulls them low). These signals are available as

status bits in a register, and any state change can also cause an interrupt informing the sys-

tem that a card has been inserted or removed.

pcm Dual-mode.

Memory Mode: These bits indicate the card battery condition as outlined in Table 2-6.

Table 2-6. PC Card Battery Voltage Detect Encoding

PCM_BVD[2:1] Battery Condition

X0

Battery dead

01

Battery low

11

Battery OK

I/O Mode: PCM_BVD[2] becomes SPKR_L, the Audio Digital Waveform signal, while

PCM_BVD[1] becomes the STSCHG_L signal, a status line that indicates state changes of

BVD, CD, and WP. The state of the BVD inputs can be read by the CPU in the CL-PS6700

Status registers and are also available on the PC Card registers.

CIRRUS LOGIC CONFIDENTIAL, NDA REQUIRED

16

PIN DESCRIPTIONS

November 1997

PRELIMINARY DATA BOOK v1.0

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