DatasheetQ Logo
Electronic component search and free download site. Transistors,MosFET ,Diode,Integrated circuits

CS5467 데이터 시트보기 (PDF) - Cirrus Logic

부품명
상세내역
제조사
CS5467
Cirrus-Logic
Cirrus Logic Cirrus-Logic
CS5467 Datasheet PDF : 46 Pages
First Prev 11 12 13 14 15 16 17 18 19 20 Next Last
CS5467
SWITCHING CHARACTERISTICS
• Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions.
• Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C.
• VA+ = 5 V ±5% VD+ = 3.3 V ±5% or 5 V ±5%; AGND = DGND = 0 V. All voltages with respect to 0 V.
• Logic Levels: Logic 0 = 0 V, Logic 1 = VD+.
Parameter
Symbol Min
Typ
Max Unit
Rise Times
(Note 17)
trise
-
-
1.0
µs
Any Digital Output
-
50
-
ns
Fall Times
(Note 17)
tfall
Any Digital Output
-
-
1.0
µs
-
50
-
ns
Start-up
Oscillator Start-up Time
XTAL = 4.096 MHz (Note 18)
tost
-
60
-
ms
Serial Port Timing
Serial Clock Frequency
SCLK
-
-
2
MHz
Serial Clock
Pulse Width High
t1
Pulse Width Low
t2
200
-
200
-
-
ns
-
ns
SDI Timing
CS Falling to SCLK Rising
t3
50
-
-
ns
Data Set-up Time Prior to SCLK Rising
t4
50
-
-
ns
Data Hold Time After SCLK Rising
t5
100
-
-
ns
SDO Timing
CS Falling to SDO Driving
t6
-
20
50
ns
SCLK Falling to New Data Bit (hold time)
t7
-
20
50
ns
CS Rising to SDO Hi-Z
t8
-
20
50
ns
E2PROM mode Timing
Serial Clock
Pulse Width Low
t9
Pulse Width High
t10
8
DCLK
8
DCLK
MODE setup time to RESET Rising
t11
50
ns
RESET rising to CS falling
t12
48
DCLK
CS falling to SCLK rising
t13
100
8
DCLK
SCLK falling to CS rising
t14
16
DCLK
CS rising to driving MODE low
t15
50
ns
SDO setup time to SCLK rising
t16
100
ns
Notes: 17. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF.
18. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an
external clock source.
DS714F1
11

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]