CS5467 데이터 시트보기 (PDF) - Cirrus Logic

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CS5467

Four-channel Power / Energy IC

Cirrus Logic 

CS5467

ANALOG CHARACTERISTICS (Continued)

Parameter

Symbol Min

Analog Inputs (Voltage Inputs)

Differential Input Range

[(VIN+) – (VIN-)]

VIN

-

Total Harmonic Distortion

THD

65

Crosstalk from Current inputs at Full Scale (50, 60 Hz)

-

Input Capacitance

Effective Input Impedance

All Gain Ranges

IC

-

EII

2

Noise (Referred to Input)

Offset Drift (Without the High-pass Filter)

NV

-

OD

-

Gain Error

Temperature

(Note 3)

GE

-

Temperature Accuracy

T

-

Power Supplies

Power Supply Currents (Active State)

IA+ PSCA

-

ID+ (VA+ = VD+ = 5 V) PSCD

-

ID+ (VA+ = 5 V, VD+ = 3.3 V) PSCD

-

Power Consumption

Active State (VA+ = VD+ = 5 V)

-

(Note 4)

Active State (VA+ = 5 V, VD+ = 3.3 V)

Stand-by State

PC

-

-

Sleep State

-

Power Supply Rejection Ratio (50, 60 Hz)

(Note 5)

Voltage

Current (Gain = 50x) PSRR

48

68

Current (Gain = 10x)

60

PFMON Low-voltage Trigger Threshold

PFMON High-voltage Power-on Trip Point

(Note 6) PMLO

2.3

(Note 7) PMHI

-

Typ

500

75

-70

2.0

-

-

16.0

±3.0

±5

1.5

3.5

2.3

25

15

7

10

55

75

65

2.45

2.55

Max Unit

-

mVP-P

-

dB

-

dB

-

pF

-

MΩ

140 µVrms

-

µV/°C

%

-

°C

-

mA

-

mA

-

mA

33

mW

20

mW

-

mW

-

uW

-

dB

-

dB

-

dB

-

V

2.7

V

Notes: 3. Applies before system calibration.

4. All outputs unloaded. All inputs CMOS level.

5. Measurement method for PSRR: VREFIN tied to VREFOUT, VA+ = VD+ = 5 V, a 150 mV

(zero-to-peak) (60 Hz) sinewave is imposed onto the +5 V DC supply voltage at VA+ and VD+ pins. The

“+” and “-” input pins of both input channels are shorted to AGND. The CS5467 is then commanded to

continuous conversion acquisition mode, and digital output data is collected for the channel under test.

The (zero-to-peak) value of the digital sinusoidal output signal is determined, and this value is converted

into the (zero-to-peak) value of the sinusoidal voltage (measured in mV) that would need to be applied

at the channel’s inputs, in order to cause the same digital sinusoidal output. This voltage is then defined

as Veq. PSRR is (in dB):

PSRR

=

20 ⋅ log

1----5---0--

Veq

6. When the voltage level on PFMON is sagging and LSD bit = 0, this is the voltage at which LSD is set to 1.

7. If the LSD bit has been set to 1 (because PFMON voltage fell below PMLO), this is the voltage level on

PFMON at which the LSD bit can be permanently reset back to 0.

8

DS714F1

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