CS5566 데이터 시트보기 (PDF) - Cirrus Logic
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CS5566 Datasheet PDF : 30 Pages
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5/4/09
CS5566
SWITCHING CHARACTERISTICS
TA = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%;
VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5%
Input levels: Logic 0 = 0V Low; Logic 1 = VD+ = High; CL = 15 pF.
Parameter
Symbol Min
Typ
Master Clock Frequency
Internal Oscillator XIN
6
7
External Clock fclk
0.5
8
Master Clock Duty Cycle
40
-
Reset
RST Low Time
tres
1
-
RST rising to RDY falling
Internal Oscillator twup
External Clock
-
240
-
3084
Conversion
CONV Pulse Width
tcpw
4
-
BP/UP setup to CONV falling
(Note 8)
tscn
0
-
CONV low to start of conversion
tscn
-
1182
Perform Single Conversion (CONV high before RDY falling)
tbus
20
-
Conversion Time
(Note 9)
Start of Conversion to RDY falling tbuh
-
-
Sleep Mode
SLEEP low to low-power state
tcon
SLEEP high to device active (Note 10) tcon
-
50
-
3083
8. BP/UP can be changed coincident CONV falling. BP/UP must remain stable until RDY falls.
9. If CONV is held low continuously, conversions occur every 1600 MCLK cycles.
If RDY is tied to CONV, conversions will occur every 1602 MCLKs.
If CONV is operated asynchronously to MCLK, a conversion may take up to 1604 MCLKs.
RDY falls at the end of conversion.
10. RDY will fall when the device is fully operational when coming out of sleep mode.
Max
8
8.1
60
-
-
-
-
-
1186
-
1604
-
-
Unit
MHz
MHz
%
µs
µs
MCLKs
MCLKs
ns
MCLKs
MCLKs
MCLKs
µs
MCLKs
tbus
CONVERT
RDY
Converter
Status
6
IDLE
1182 - 1186 MCLKs
1600 - 1604 MCLKs
CONVERT
354 + 64 MCLKs
SDO
ACTIVE
Figure 1. Converter Status (Not to scale)
IDLE
DS806PP2
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