CS61584A 데이터 시트보기 (PDF) - Cirrus Logic

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CS61584A

Dual T1/E1 Line Interface

Cirrus Logic 

DS261PP5

CS61584A

response to a Loss of Signal condition for either

channel is activated by setting bit 1 of the channel

1 Mask register to 1.

8.8 Local Loopback

Selecting LLOOP causes the TCLK, TPOS, and

TNEG (or TDATA) inputs to be looped back

through the jitter attenuator (if enabled) to the

RCLK, RPOS, and RNEG (or RDATA) outputs.

The receive line interface is ignored, but data at

TPOS and TNEG (or TDATA) continues to be

transmitted to the line interface at TTIP and

TRING. During Hardware mode operation, simul-

taneous local loopback 2 of both channels is select-

ed by setting the LLOOP pin high. During Host

mode operation, local loopback 1 on a per channel

basis is controlled using the LLOOP1 bit in the

Control B registers.

During Hardware mode operation, a per channel lo-

cal loopback 1 is performed when both the RLOOP

and TAOS pins are high. The data at TPOS and

TNEG is overridden with an all-ones pattern (TAOS)

and the receive input at RTIP and RRING is ignored.

During Host mode operation, local loopback 2 can

also be selected using the LLOOP2 bit in the Control

B registers. Selecting LLOOP2 causes the TCLK,

TPOS, and TNEG (or TDATA) inputs to be looped

back to the RCLK, RPOS, and RNEG (or RDATA)

outputs. The line driver, line receiver, and jitter at-

tenuator (if enabled) are also included. The receive

line interface is ignored, but data at TPOS and

TNEG (or TDATA) continues to be transmitted to

the line interface at TTIP and TRING.

A TAOS request overrides the data transmitted to

the line interface during both local loopbacks. A

TAOS request also overrides the data received at

RPOS and RNEG (or RDATA) during local loop-

back 2. Note that simultaneous selection of local

and remote loopback modes is not valid.

8.9 Remote Loopback

During Hardware mode operation, remote loop-

backs of either channel is selected by setting the

RLOOP pin high. During Host mode operation, re-

mote loopback of each channel is controlled using

the RLOOP bit in the Control B registers.

Selecting RLOOP causes the data received from

the line interface at RTIP and RRING to be looped

back through the jitter attenuator (if enabled) and

retransmitted on TTIP and TRING. Data input to

TPOS and TNEG (or TDATA) is ignored, but data

recovered from RTIP and RRING continues to be

output on RPOS and RNEG (or RDATA).

Remote loopback is functional if TCLK is absent.

A TAOS request overrides the data transmitted to

the line interface during a remote loopback. Note

that simultaneous selection of local and remote

loopback modes is not valid.

8.10 Driver Tristate

The drivers may be independently tristated in all

modes of operation. During Hardware mode opera-

tion, setting the CON[3:0] pins of a channel to

"111X" will tristate the driver. During Host mode se-

rial port operation, the ZTX1 and ZTX2 pins perform

the driver tristate function and setting the CON[3:0]

bits in the Control B registers to "111X" will also

tristate the driver. During Host mode parallel port op-

eration, setting the CON[3:0] bits in the Control B

register to "111X" tristates the driver. In host mode,

the CS61584A powers up with CON[3:0] set to

1110, which tristates the transmitter.

8.11 Power Down

During Hardware mode operation, channel power

down is selected by setting the PD1 or PD2 pin

high. During Host mode operation, channel power

down is controlled using the PD bit in the Control

A registers. Power down places the transmitter, re-

ceiver, and jitter attenuator in reset. The RCLK,

RPOS, RNEG, RDATA, AIS, BPV, TTIP, and

TRING output pins are placed in a high-impedance

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DDS2S6216P1PF15

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