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CS61584A

Dual T1/E1 Line Interface

Cirrus Logic 

DS261PP5

CS61584A

state. LOS will go high, and the status register will

be reset, but the Control, Mask, and Arbitrary

Waveform registers remain unchanged. The chan-

nel not in power down and the processor port will

still to operate normally.

Simultaneously selecting PD1 and PD2 will place

all the above-mentioned pins in high impedance

state and power down additional analog circuitry

that is shared by both channels. The status registers

are reset. In the hardware mode all output pins are

tri-stated and internally pulled up to the positive

supply rail. After exiting the power down state, the

channel will be fully operational in less than 20 ms.

8.12 Reset Pin

The CS61584A is continuously calibrated during

operation to insure the performance of the device

over power supply and temperature. This continu-

ous calibration function eliminates the need to reset

the line interface during operation.

During Hardware and Host modes of operation, a

device reset is selected by setting the RESET pin

high for a minimum of 200 ns. The reset function

initiates on the falling edge of RESET and requires

less than 20 ms to complete. The control logic and

register set are initialized and the transmit and re-

ceive circuitry is calibrated if REFCLK and TCLK

are present. During Host mode operation, a reset

event is indicated by the Latched-Reset bit in the

Status register.

9. HOST MODE

Host mode allows the CS61584A to be configured

and monitored using an internal register set. This

option is selected when the MODE pin is set high.

Using the P/S pin, serial or 8-bit parallel interface

ports are available in Host mode. During serial port

operation, the registers are specified by a 6-bit ad-

dress in the range of 0x10 to 0x19. During parallel

port operation, the registers are specified by an 8-

bit address. The four most significant bits of the ad-

dress selects one of 16 devices on the board, estab-

lished by the SAD[7:4] pins. The four least

significant bits of the address specify the register

address in the range of 0x00 to 0x09 for the selected

device. Parallel port option is compatible with Mo-

torola and Intel 8-bit, multiplexed address/data bus.

9.1 Register Set

The register set available during Host mode opera-

tion is presented in Table 4.

Serial Port Parallel Port

Description

Address Address*

0x10

0xY0 Ch 1 Status

0x11

0xY1 Ch 2 Status

0x12

0xY2 Ch 1 Mask

0x13

0xY3 Ch 2 Mask

0x14

0xY4 Ch 1 Control A

0x15

0xY5 Ch 2 Control A

0x16

0xY6 Ch 1 Control B

0x17

0xY7 Ch 2 Control B

0x18

0xY8 Ch 1 Arbitrary Pulse Shape

0x19

0xY9 Ch 2 Arbitrary Pulse Shape

*Y denotes the SAD[7:4] address of the CS61584A device.

Table 4. CS61584A Register Set

9.1.1 Status Registers

The Status registers are read-only registers and are

shown in Table 5. The CS61584A generates an in-

terrupt on the INT pin any time an unmasked Status

register bit changes. When BTS is low (Intel

mode), the IPOL pin determines the polarity of the

INT pin. When BTS is high (Motorola mode), INT

polarity is active low (IPOL becomes DTACK).

Reading both Status register clears the interrupt

and deactivates the INT pin.

LOS: Set high while the loss of signal condition is

detected. Reading the Status register does not clear

the LOS bit. A LOS interrupt is generated only on

the falling edge of the LOS alarm condition. The

Latched-LOS bit generates an interrupt on the ris-

ing edge of LOS. Refer to the timing diagram in

Figure 18.

DS261FP1P5

23

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