CS61310(2003) 데이터 시트보기 (PDF) - Cirrus Logic

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CS61310
(Rev.:2003)

T1 Line Interface Unit

Cirrus Logic 

CS61310

2.5 Jitter Attenuator

Jitter attenuation can be implemented in either the

transmit (JASEL low) or receive (JASEL high)

paths, or it can be eliminated from the circuit by

setting the XTALIN pin high. The jitter attenuator

on the CS61310 does not require a crystal. It is ac-

tivated when XTALIN is either connected to ground

or left open; connecting to ground is the preferred

method.

The jitter attenuator corner frequency is set at

4 Hz, with attenuation increasing at a 20 dB per

decade rate above 4 Hz. A typical jitter attenuation

graph is shown in Figure 8.

2.6 Receiver Line Attenuation Indication

The LATN pin outputs a coded signal that repre-

sents the signal level at the input of the receiver. As

shown in Figure 9, the LATN output is measured

against RCLK to provide the signal level in 7.5 dB

increments. In host mode, the receive input signal

level can be read from the Equalizer Gain register,

address 0x12, to greater resolution, dividing the in-

put range into 20 steps of 2 dB increments.

0

M inimum A ttenuation Lim it

10

20

62411 Requirem ents

30

40 Maximum

A tte n u a tio n

50 Lim it

60

M easured Perform ance

1

10

100

1k

10 k

Frequency in Hz

Figure 8. Typical Jitter Transfer Function

2.7 Receiver Loss of Signal

The receiver will indicate loss of signal by setting

the LOS pin high in hardware mode (CR1.0 = 1 in

host mode). LOS is active on power up, reset,

when receiver gain is maximized, upon receiving

175+/-15 consecutive zeros, or when the received

signal power falls below below the signal level,

“Loss of Signal Threshold” listed under Analog

Specifications. Received zeros are counted based

on recovered clock cycles. While in the LOS state,

received data on RPOS/RNEG (RDATA in unipolar

mode) equals 0 (squelched). The device complies

with ANSI T1.231-1993 criteria to exit the LOS

condition: 12.5% ones density for 175+/-75 bit pe-

riods with no more than 100 consecutive zeros.

While LOS is active, RCLK depends on MCLK and

the jitter attenuator. If the jitter attenuator is in the

transmit path or not used, RCLK is referenced to

MCLK, if provided, or the crystal oscillator other-

wise. If the jitter attenuator is in the receive path,

the jitter attenuator will hold the average incoming

data frequency prior to LOS. The recovered clock

remains at a 50% duty cycle. The RPOS (RDATA)

and RNEG pins are forced low during LOS.

Timing is recovered by a phase selector which se-

lects one of the phases from the internal synchro-

nization clock (one of three clocks, 120 degrees

apart in phase, at 16X of the data rate). Since the

selection is made between a limited set of phases,

the Digital Timing Recovery process has a small

phase error built into the sampling process. By

choosing from 48 possible sampling phases, the

CS61310 reduces the sampling error to a mini-

mum.

RCLK

LATN

1

2

3

4

5

LATN = 1 R C LK, 7.5 dB of Attenuation

LATN = 2 R C LK , 15 dB of Attenuation

LATN = 3 R C LK , 22.5 dB of A ttenuation

LA TN = 4 RC LK , 0 dB of Attenuation

Figure 9. LATN Pulse Width encoding

DS440F1 FEB ‘03

11

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