CS98100 데이터 시트보기 (PDF) - Cirrus Logic

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CS98100

DVD Processor for Low Cost DVD Players

Cirrus Logic 

CS98100

1.2.2 SDRAM Interface

The CS98100 interfaces with either SDRAM or SGRAM, for high data bandwidth transfer. Figure 5 and

Table 2 show the interface pin timing. Figure 2 shows the refresh cycle performed by the CS98100.

Figure 3 shows a burst read (length = 8) transaction, while Figure 4 shows a burst write (length=8) trans-

action. In both Figure 3 and Figure 4, CAS latency is programmed to 3.

Symbol

tmco

tmper

tmdow

tmhw

tmsur1

tmsurd1

tmhr1

tmhrd1

Description

Min

Output Delay from DR_CKO active edge

DR_CKO Period

11

DR_D[31:0] delay from DR_CKO

DR_D[31:0] valid time after DR_CKO

1.5

DR_D[31:0] setup to DR_CKO

3.9

DR_D[31:0] setup to DR_CKO with delay 4.3

DR_D[31:0] hold time after DR_CKO

1.85

DR_D[31:0] hold time after DR_CKO with 1.3

delay

Typ

12.2

Max

9

9.1

Unit

ns

ns

ns

ns

ns

ns

ns

ns

Table 2. SDRAM Interface Characteristics

1.Delay is programmable by selecting the DRAM_Input_Speed bit of the Command Register(0x000)

DR_CKO

DR_A[11:0]

DR_BS_N

DR_RAS_N

DR_CAS_N

DR_WE_N

DR_D[31:0]

DR_DQM_[3:0]

DR_AP

Figure 2. SDRAM Refresh Transaction

8

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