CXA2025 데이터 시트보기 (PDF) - Sony Semiconductor

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CXA2025

Y/C/RGB/Sync/Deflection for Color TV

Sony Semiconductor 

CXA2025AS

Pin

No.

Symbol

33 SAWOSC

Equivalent circuit

Description

JVCC

100

100

33

Connect a capacitor to generate the V sawtooth

wave.

100µ

34 JVCC

35 HDRIVE

JVCC

147

35

20k

Power supply for the deflection block.

H drive signal output.

This signal is output with the open collector.

This pin goes high (OFF) during hold-down.

∗ For the CXA2025S, this pin is low (ON) during

hold-down.

36

AFCPIN

/HOFF

37 L2FIL

38 AFCFIL

39 CERA

40 JGND

H deflection pulse input for H AFC.

JVCC Input an about 5Vp-p pulse via a capacitor. Set

the pulse width to 10 to 12µs. This pin is also

147 10k

60k

36

4.2V used as the hold-down signal input for the HD

output, and if this pin is 1 [V] or less for a 7V

50µ 50µ

cycle or longer, the hold-down function operates

and the HD output goes to high (OFF).

10k

In addition, the RGB outputs are all blanked and

the status is returned to the I2C bus.

JVCC

Filter for H AFC.

Connect to GND via a capacitor. The H phase

100

37

can also be controlled from this pin by leading

current in and out of this capacitor.

As the pin voltage rises, the picture shifts to the

25µ

left; as the pin voltage drops, the picture shifts to

the right.

JVCC

1.2k

46k

38

50µ

50µ

CR connection for the AFC lag-lead filter.

JVCC

10k

39

400µ

50µ

Connect the 32fH VCO ceramic oscillator.

GND for the deflection block.

–7–

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