CXA2025 데이터 시트보기 (PDF) - Sony Semiconductor

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CXA2025

Y/C/RGB/Sync/Deflection for Color TV

Sony Semiconductor 

Pin

No.

Symbol

41 IREF

Equivalent circuit

JVCC

147

20k

41

CXA2025AS

Description

Internal reference current setting.

Connect to GND via a 15kΩ resistor.

42 VSFIL

JVCC

42

1k

Filter for V sync separation.

Connect to GND via a capacitor.

43 VSIN

44 HSIN

45 VM

46 BGP

47 GND

48 GND

JVCC

147

43

20µ

Sync signal input for V sync separation.

Input a 2Vp-p Y signal.

JVCC

147

44

10µ

Sync signal input for H sync separation.

Input a 2Vp-p Y signal.

SVCC

Outputs the differential waveform of the VM

(Velocity Modulation) Y signal. (7.1VDC, 2.0Vp-p)

The signal delayed for 250ns from YIN is output.

45

The delay time from YIN and the differential

coefficient of the output signal vary according to

400µ

sharpness f0 control.

1k

46

15k

1k

Burst gate pulse output.

This pulse is a 0 to 3V positive polarity pulse.

While this pulse is gated near V-Sync for the

CXA2025S, it is constantly output for the

CXA2025AS.

Not connected.

Normally connected to GND to prevent

interference with other pins.

–8–

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