CXA3086 데이터 시트보기 (PDF) - Sony Semiconductor
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CXA3086 Datasheet PDF : 30 Pages
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CXA3086Q
Pin
No.
Symbol
I/O
Standard
voltage level
27 CLK/T
I
Equivalent circuit
DVCC1
r/2
TTL
10 RESETN/T I
10 27
DGND1
DVEE3
1.5V
r
42 INV
I
DVCC1
44 PS
TTL
42 44
I
DGND1
DVEE3
DVCC1
Description
Clock input.
Reset input.
When left open, this input goes to
high level. When the input is set to
low level, the built-in CLK frequency
divider circuit can be reset.
Data output polarity inversion input.
When left open, this input goes to
high level.
(See Table 1. I/O Correspondence
Table.)
Power saving input.
When the input is set to low level,
the power saving mode is set.
In this time the all TTL outputs go
into the high-impedance state.
Normally, set to high level or left
open.
41 SELECT
Vcc
or
GND
22 VRTS
O
+4.0V
(typ.)
21 VRT
I
VRTS
+r1 x Iref
16 VRB
I
VRBS
–r2 x Iref
15 VRBS
O
+2.0V
(typ.)
41
DGND1
DVEE3
Data output mode selection.
(See Table 2. Operating Mode
Table.)
22
r1
21
r
r
r
r
Comparator 1
Comparator 2
r
r
r
r2 r
16
15
Comparator 62
Comparator 63
Reference voltage sense.
By-pass to AGND with a 0.1µF chip
capacitor.
Top reference voltage.
By-pass to AGND with a 1µF tantal
capacitor and a 0.1µF chip
capacitor.
Bottom reference voltage.
By-pass to AGND with a 1µF tantal
capacitor and a 0.1µF chip
capacitor.
Reference voltage sense.
By-pass to AGND with a 0.1µF chip
capacitor.
–5–
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