CXD1172 데이터 시트보기 (PDF) - Sony Semiconductor

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CXD1172

6-bit 20MSPS Video A/D Converter (CMOS)

Sony Semiconductor 

CXD1172AM/AP

Operation (See Block Diagram and Timing Chart)

1. CXD1172AM/AP is a 2-step parallel system A/D converter featuring a 3-bit upper comparators group and 2

Iower comparators groups of 3-bit each. The reference voltage that is equal to the voltage between VRT-

VRB/8 is constantly applied to the upper 3-bit comparator block. Voltage that corresponded to the upper

data is fed through the reference supply to the lower data.

2. This IC uses an offset cancel type comparator and operates synchronously with an external clock. It features

the following operating modes which are respectively indicated on the timing chart with S, H, C symbols.

That is input sampling (auto zero) mode, input hold mode and comparison mode.

3. The operation of respective parts is as indicated in the chart. For instance input voltage Vi (1) is sampled with

the falling edge of the first clock by means of the upper comparator block and the Iower comparator A block.

The upper comparators block finalizes comparison data MD (1) with the rising edge of the first clock.

Simultaneously the reference supply generates the lower reference voltage RV (1) that corresponded to the

upper results. The lower comparator block finalizes comparison data LD (1) with the rising edge of the

second clock. MD (1) and LD (1) are combined and output as Out (1) with the rising edge of the 3rd clock.

Accordingly there is a 2.5 clock delay from the analog input sampling point to the digital data output.

Operation Notes

1. VDD, Vss

To reduce noise effects, separate the analog and digital systems close to the device. For both the digital and

analog VDD pins, use a ceramic capacitor of about 0.1µF set as close as possible to the pin to bypass to the

respective GND's.

2. Analog input

Compared with the flash type A/D converter, the input capacitance of the analog input is rather small.

However it is necessary to conduct the drive with an amplifier featuring sufficient band and drive capability.

When driving with an amplifier of low output impedance, parasite oscillation may occur. That may be

prevented by inserting a resistance of about 100Ω in series between the amplifier output and A/D input.

3. Clock input

The clock line wiring should be as short as possible also, to avoid any interference with other signals,

separate it from other circuits.

4. Reference input

Voltage between VRT to VRB is compatible with the dynamic range of the analog input. Bypassing VRT and

VRB pins to GND, by means of a capacitor about 0.1µF, stable characteristics are obtained.

5. Timing

Analog input is sampled with the falling edge of CLK and output as digital data with a delay of 2.5 clocks and

with the following rising edge. The delay from the clock rising edge to the data output is about 18ns.

6. About latch up

It is necessary that AVDD and DVDD pins be the common source of power supply.

This is to avoid latch up due to the voltage difference between AVDD and DVDD pins when power is ON.

See "For latch up prevention" of CXD1172P/CXA1106P PCB description. (Page 6, 7)

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