CXD2311AR
Digital Output
The following table shows the correlation between the analog input voltage and the digital output code
(TESTMODE = 1, LINV, MINV = 0)
Input signal voltage
Step
Digital output code
MSB
LSB
VRT
0
1111111111
511 1 0 0 0 0 0 0 0 0 0
512 0 1 1 1 1 1 1 1 1 1
VRB
1023 0 0 0 0 0 0 0 0 0 0
The following table shows the output state for the combination of TESTMODE, LINV, and MINV states.
TESTMODE LINV MINV D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
1
0
0 PPPPPPPPPP
1
1
0 NNNNNNNNNP
1
0
1 PPPPPPPPPN
1
1
1 NNNNNNNNNN
0
0
0 1010101010
0
1
0 0101010100
0
0
1 1010101011
0
1
1 0101010101
P: Forward-phase output N: Inverted output
Timing Chart 1
tPW1
tPW0
Clock
1.65V
tSH
tSL
Analog input
HOLD N
tDL
Data output
HOLD N + 1
N–3
N–2
HOLD N + 2
HOLD N + 3
N–1
N
Timing Chart 2
Output enable (OE)
1.65V (DVDD = 3.3V)
2.5V (DVDD = 5.0V)
tPEZ
1.65V
tPZE
1.65V (DVDD = 3.3V)
2.5V (DVDD = 5.0V)
1.65V
Data output
Active
High Impedance
–6–
Active