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CY14B101J

1-Mbit (128 K × 8) Serial (I2C) nvSRAM

Cypress Semiconductor 

CY14C101J

CY14B101J

CY14E101J

Figure 6. Acknowledge on the I2C Bus

handbook, full pagewidth

DATA OUTPUT

BY MASTER

DATA OUTPUT

BY SLAVE

not acknowledge (A)

acknowledge (A)

SCL FROM

MASTER

S

1

2

START

condition

8

9

clock pulse for

acknowledgement

High-Speed Mode (Hs-mode)

In Hs-mode, nvSRAM can transfer data at bit rates of up to

3.4 Mbit/s. A master code (0000 1XXXb) must be issued to place

the device into high speed mode. This enables master slave

communication for speed upto 3.4 MHz. A stop condition exits

Hs-mode.

Serial Data Format in Hs-mode

Serial data transfer format in Hs-mode meets the standard-mode

I2C-bus specification. Hs-mode can only commence after the

following conditions (all of which are in F/S-modes):

1. START condition (S)

2. 8-bit master code (0000 1XXXb)

3. No-acknowledge bit (A)

handbook, full pagewidth

F/S-mode

Figure 7. Data transfer format in Hs-mode

Hs-mode

F/S-mode

S MASTER CODE A Sr SLAVE ADD. R/W A

DATA

A/A P

n (bytes+ack.)

Hs-mode continues

Sr SLAVE ADD.

Single and multiple-byte reads and writes are supported. After

the device enters into Hs-mode, data transfer continues in

Hs-mode until stop condition is sent by master device. The slave

switches back to F/S-mode after a STOP condition (P). To

continue data transfer in Hs-mode, the master sends Repeated

START (Sr).

See Figure 13 on page 11 and Figure 16 on page 12 for Hs-mode

timings for read and write operation.

Document Number: 001-54050 Rev. *M

Page 6 of 31

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