CY14B101L-SZ25XC 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY14B101L-SZ25XC Datasheet PDF : 18 Pages
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Table 2. Hardware Mode Selection
CE
WE
OE
H
X
X
L
H
L
L
L
X
L
H
L
L
H
L
L
H
L
L
H
L
CY14B101L
A15 – A0
X
X
X
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8B45
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4B46
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8FC0
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4C63
Mode
Not Selected
Read SRAM
Write SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore Disable
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore Enable
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile Store
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile Recall
IO
Power
Output High Z
Output Data
Standby
Active[3]
Input Data
Active
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active[1, 2, 3]
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active[1, 2, 3]
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active ICC2[1, 2, 3]
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active[1, 2, 3]
Notes
1. The six consecutive address locations are in the order listed. WE is HIGH during all six cycles to enable a nonvolatile cycle.
2. While there are 17 address lines on the CY14B101L, only the lower 16 lines are used to control software modes.
3. IO state depends on the state of OE. The IO table shown is based on OE Low.
Document Number: 001-06400 Rev. *J
Page 6 of 18
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