CY14C101I(2012) 데이터 시트보기 (PDF) - Cypress Semiconductor

부품명

상세내역

제조사

CY14C101I
(Rev.:2012)

1-Mbit (128 K × 8) Serial (I2C) nvSRAM with Real Time Clock

Cypress Semiconductor 

PRELIMINARY

CY14C101I

CY14B101I

CY14E101I

Figure 5. Acknowledge on the I2C Bus

handbook, full pagewidth

DATA OUTPUT

BY MASTER

DATA OUTPUT

BY SLAVE

Not acknowledge (A)

Acknowledge (A)

SCL FROM

MASTER

1

S

START

Condition

High-Speed Mode (Hs-mode)

In Hs-mode, nvSRAM can transfer data at bit rates of up to

3.4 Mbit/s. A master code (0000 1XXXb) must be issued to place

the device in high-speed mode. This enables master/slave

communication for speeds up to 3.4 MHz. A stop condition will

exit Hs-mode.

Serial Data Format in Hs-mode

Serial data transfer format in Hs-mode meets the standard-mode

I2C-bus specification. Hs-mode can only commence after the

following conditions (all of which are in F/S-modes):

2

8

9

Clock pulse for

acknowledgement

1. START condition (S)

2. 8-bit master code (0000 1XXXb)

3. No-acknowledge bit (A)

Single and multiple-byte reads and writes are supported. After

the device enters into Hs-mode, data transfer continues in

Hs-mode until stop condition is sent by master device. The slave

switches back to F/S-mode after a STOP condition (P). To

continue data transfer in Hs-mode, the master sends Repeated

START (Sr).

See Figure 13 on page 11 and Figure 16 on page 12 for Hs-mode

timings for read and write operation.

handbook, full pagewidth

F/S-mode

Figure 6. Data Transfer Format in Hs-mode

Hs-mode

F/S-mode

S MASTER CODE A Sr SLAVE ADD. R/W A

DATA

A/A P

n (bytes+ack.)

Hs-mode continues

Sr SLAVE ADD.

Document Number: 001-54391 Rev. *G

Page 6 of 41

Share Link: