CY14C101Q3 데이터 시트보기 (PDF) - Cypress Semiconductor

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CY14C101Q3

1-Mbit (128 K × 8) Serial (SPI) nvSRAM

Cypress Semiconductor 

CY14C101Q

CY14B101Q, CY14E101Q

Figure 7. Read Status Register (RDSR) Instruction Timing

CS

SCK

SI

0 1 2 3 4 5 67 01 2 3 4 5 67

Op-Code

0 0 0 0 01 0 1 0

CS

SCK

SI

SO

HI-Z

D7 D6 D5 D4 D3 D2 D1 D0

MSB

Data

LSB

Figure 8. Fast Read Status Register (FAST_RDSR) Instruction Timing

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7

Op-Code

Dummy Byte

0 0 0 0 1 00 1 XXXXX XXX 0

SO

HI-Z

D7 D6 D5 D4 D3 D2 D1 D0

MSB

Data

LSB

Figure 9. Write Status Register (WRSR) Instruction Timing

CS

SCK

SI

SO

01 23 4 5 6 701 2 3 4 5 6 7

Opcode

Data in

0 0 0 0 0 0 0 1 D7 X X X D3 D2 X X

MSB

LSB

HI-Z

Document #: 001-54393 Rev. *F

Page 11 of 34

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