CY14B256KA-SP25XIT(2009) 데이터 시트보기 (PDF) - Cypress Semiconductor

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CY14B256KA-SP25XIT
(Rev.:2009)

256 Kbit (32K x 8) nvSRAM with Real Time Clock

Cypress Semiconductor 

CY14B256KA

Pinouts

Figure 1. Pin Diagram - 48-Pin SSOP

VCAP

NC[1]

1

2

A14 3

A12 4

A7 5

A6 6

A5 7

INT 8

A4 9

48 VCC

47 NC[1]

46 HSB

45 WE

44 A13

43 A8

42 A9

41 NC

48 - SSOP 40 A11

NC 10

(x8)

39 NC

NC 11 Top View

38 NC

NC

VSS

12

13

(not to scale)

37

36

NC

VSS

NC 14

35 NC

VRTCbat

15

34

VRTCcap

DQ0 16

33 DQ6

A3 17

32 OE

A2 18

A1 19

A0 20

31 A10

30 CE

29 DQ7

DQ1 21

DQ2 22

Xout 23

28 DQ5

27 DQ4

26 DQ3

Xin 24

25 VCC

Pin Definitions

Pin Name I/O Type

Description

A0 – A14

DQ0 – DQ7

NC

Input

Input/Output

No Connect

Address Inputs Used to Select One of the 32,768 Bytes of the nvSRAM.

Bidirectional Data I/O Lines. Used as input or output lines depending on operation.

No Connects. This pin is not connected to the die.

WE

Input

Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the I/O pins is

written to the specific address location.

CE

Input Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.

Input Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read

OE

cycles. Deasserting OE HIGH causes the I/O pins to tristate.

Xout

Xin

VRTCcap

VRTCbat

Output Crystal Connection. Drives crystal on start up.

Input Crystal Connection. For 32.768 kHz crystal.

Power Supply Capacitor Supplied Backup RTC Supply Voltage. Left unconnected if VRTCbat is used.

Power Supply Battery Supplied Backup RTC Supply Voltage. Left unconnected if VRTCcap is used.

Notes

1. Address expansion for 1 Mbit. NC pin not connected to die.

Document #: 001-55720 Rev. *A

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