CY14B256L(2007) 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY14B256L Datasheet PDF : 17 Pages
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PRELIMINARY
CY14B256L
AutoStore/Power Up RECALL
Parameter
Description
tHRECALL [12]
tSTORE [13, 14]
VSWITCH
tVCCRISE
Power Up RECALL Duration
STORE Cycle Duration
Low Voltage Trigger Level
VCC Rise Time
Software Controlled STORE/RECALL Cycle [15, 16]
Parameter
Description
tRC
tAS
tCW
tGHAX
tRECALL
tSS[17, 18]
STORE/RECALL Initiation Cycle Time
Address Setup Time
Clock Pulse Width
Address Hold Time
RECALL Duration
Soft Sequence Processing Time
Hardware STORE Cycle
Parameter
Description
tDELAY [19]
tHLHX
Time allowed to complete SRAM Cycle
Hardware STORE Pulse Width
CY14B256L
Unit
Min
Max
20
ms
12.5
ms
2.65
V
150
µs
25 ns part
Min Max
25
0
20
1
50
70
35 ns part
Min Max
35
0
25
1
50
70
45 ns part
Unit
Min Max
45
ns
0
ns
30
ns
1
ns
50 µs
70 µs
CY14B256L
Unit
Min
Max
1
70
µs
15
ns
Notes
11. If WE is low when CE goes low, the outputs remain in the high impedance state.
12. tHRECALL starts from the time VCC rises above VSWITCH.
13. If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE takes place.
14. Industrial grade devices require 15 ms max.
15. The software sequence is clocked with CE-controlled or OE-controlled READs.
16. The six consecutive addresses must be read in the order listed in the Table 1,Mode Selection, on page 5. WE must be HIGH during all six consecutive cycles.
17. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register the command.
18. Commands like STORE and RECALL lock out IO until operation is complete which further increases this time. See the specific command.
19. READ and WRITE cycles in progress before HSB are given this amount of time to complete.
Document #: 001-06422 Rev. *E
Page 10 of 17
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