CY14B256P 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY14B256P Datasheet PDF : 36 Pages
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CY14B256P
Figure 7. Write Status Register (WRSR) Instruction Timing
CS
SCK
SI
SO
01 23 4 5 6 701 2 3 4 5 6 7
Opcode
Data in
0 0 0 0 0 0 0 1 D7 X X X D3 D2 X X
MSB
LSB
HI-Z
Write Protection and Block Protection
CY14B256P provides features for both software and hardware
write protection using WRDI instruction and WP. Additionally, this
device also provides block protection mechanism through BP0
and BP1 pins of the Status Register.
The write enable and disable status of the device is indicated by
WEN bit of the Status Register. The write instructions (WRSR,
WRITE, and WRTC) and nvSRAM special instruction (STORE,
RECALL, ASENB, ASDISB) need the write to be enabled (WEN
bit = 1) before they can be issued.
Write Enable (WREN) Instruction
On power-up, the device is always in the write disable state. The
following WRITE, WRSR, WRTC, or nvSRAM special instruction
must therefore be preceded by a Write Enable instruction. If the
device is not write enabled (WEN = ‘0’), it ignores the write
instructions and returns to the standby state when CS is brought
HIGH. A new CS falling edge is required to re-initiate serial
communication. The instruction is issued following the falling
edge of CS. When this instruction is used, the WEN bit of Status
Register is set to ‘1’. WEN bit defaults to ‘0’ on power-up.
Note After completion of a write instruction (WRSR, WRITE, or
WRTC) or nvSRAM special instruction (STORE, RECALL,
ASENB, ASDISB) instruction, WEN bit is cleared to ‘0’. This is
done to provide protection from any inadvertent writes.
Therefore, WREN instruction must be used before a new write
instruction is issued.
Figure 8. WREN Instruction
CS
SCK
01 234567
SI
00000110
SO
HI-Z
Write Disable (WRDI) Instruction
Write Disable instruction disables the write by clearing the WEN
bit to ‘0’ to protect the device against inadvertent writes. This
instruction is issued following the falling edge of CS followed by
opcode for WRDI instruction. The WEN bit is cleared on the
rising edge of CS following a WRDI instruction.
Figure 9. WRDI Instruction
CS
SCK
01 234567
SI
00000100
SO
HI-Z
Block Protection
Block protection is provided using the BP0 and BP1 pins of the
Status Register. These bits can be set using WRSR instruction
and probed using the RDSR instruction. The nvSRAM is divided
into four array segments. One-quarter, one-half, or all of the
memory segments can be protected. Any data within the
protected segment is read only. Table 5 shows the function of
block protect bits.
Table 5. Block Write Protect Bits
Level
0
Status Register Bits
BP1
BP0 Array Addresses Protected
0
0
None
1 (1/4)
0
1
0x6000-0x7FFF
2 (1/2)
1
0
0x4000-0x7FFF
3 (All)
1
1
0x0000-0x7FFF
Document Number: 001-53881 Rev. *F
Page 10 of 36
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