CY2213 데이터 시트보기 (PDF) - Cypress Semiconductor
부품명
상세내역
제조사
CY2213 Datasheet PDF : 10 Pages
| |||
CY2213
State Transition Characteristics
Specifies the maximum settling time of the CLK and CLKB
outputs from device power-up. For VDD and VDDX any
sequences are allowed to power-up and power-down the
CY2213.
From
To
Transition Latency
Description
VDD/VDDX On CLK/CLKB Normal
3 ms
Time from VDD/VDDX is applied and settled to CLK/CLKB outputs settled.
AC Device Characteristics
Parameter
tCYCLE
tJCRMS
tJCPK
tJPRMS
tJPPK
tJLT
tJLT
tJLT
Phase Noise
DC
tDC,ERR
tCR, tCF
BWLOOP
Description
Clock cycle time
Cycle-to-cycle RMS jitter
At 125-MHz frequency
At 400-/500-MHz frequency
Cycle-to-cycle jitter (pk-pk)
At 125-MHz frequency
At 200-MHz frequency, XF = 25 MHz
At 400-/500-MHz frequency
Period jitter RMS
At 125-MHz frequency
At 400-/500-MHz frequency
Period jitter (pk-pk)
At 125-MHz frequency
At 200-MHz frequency, XF = 25 MHz
At 400-/500-MHz frequency
Long term RMS Jitter (P < 20)
At 125-MHz frequency
At 400-/500-MHz frequency
Long term RMS Jitter (20 < P < 40)
At 125-MHz frequency
At 400-/500-MHz frequency
Long-term RMS Jitter (40 < P < 60)
At 125-MHz frequency
At 400-/500-MHz frequency
Phase Noise at 10 kHz (x8 mode) @ 125 MHz
Long-term average output duty cycle
Cycle-cycle duty cycle error at x8 with
15.625-MHz input
Output rise and fall times (measured at 20% –
80% of VOHmin and VOLmax)
PLL Loop Bandwidth
Min.
2.50 (400 MHz)
–107
45
100
50 kHz (–3 dB)
Max.
8.00 (125 MHz)
0.25%
20
6.25/5
1.75%
140
55
43.75/35
0.25%
20
6.25/5
2.0%
160
65
50/40
1.75%
140
43.75/35
2.5%
200
62.5/50
3.5%
280
87.5/70
–92
55
70
400
8 MHz (–20 dB)
Unit
ns
% tCYCLE
ps
ps
% tCYCLE
ps
ps
ps
% tCYCLE
ps
ps
% tCYCLE
ps
ps
ps
% tCYCLE
ps
ps
% tCYCLE
ps
ps
% tCYCLE
ps
ps
dBc
%
ps
ps
Document #: 38-07263 Rev. *E
Page 5 of 10
Share Link: 