CY22150FCT 데이터 시트보기 (PDF) - Cypress Semiconductor

부품명

상세내역

제조사

CY22150FCT

One-PLL General-Purpose Flash-Programmable and 2-Wire Serially Programmable Clock Generator

Cypress Semiconductor 

CY22150

Frequency Calculation and Register Definitions

The CY22150 is an extremely flexible clock generator with four

basic variables that are used to determine the final output

frequency. They are the input reference frequency (REF), the

internally calculated P and Q dividers, and the post divider, which

can be a fixed or calculated value. There are three formulas to

determine the final output frequency of a CY22150 based

design:

■ CLK = ((REF * P)/Q)/Post Divider

■ CLK = REF/Post Divider

■ CLK = REF.

The basic PLL block diagram is shown in Figure 2. Each of the

six clock outputs on the CY22150 has a total of seven output

options available to it. There are six post divider options

available: /2 (two of these), /3, /4, /DIV1N and /DIV2N. DIV1N

and DIV2N are independently calculated and are applied to

individual output groups. The post divider options can be applied

to the calculated VCO frequency ((REF*P)/Q) or to the REF

directly.

In addition to the six post divider output options, the seventh

option bypasses the PLL and passes the REF directly to the

crosspoint switch matrix.

Figure 2. Basic Block Diagram of CY22150 PLL

DIV1N [OCH]

DIV1SRC [OCH]

REF

Qtotal

(Q+2)

[42H]

PFD

VCO

Ptotal

(2(PB+4)+PO)

[40H], [41H], [42H]

CLKSRC

Crosspoint

1

Switch Matrix

/DIV1N

[44H]

LCLK1

0

/2

[44H]

[44H,45H]

LCLK2

LCLK3

/3

[45H]

LCLK4

Divider Bank 1

1

Divider Bank 2

/4

0

/2

[45H]

[45H,46H]

CLK5

CLK6

/DIV2N

DIV2SRC [47H]

DIV2N [47H]

CLKOE [09H]

Document #: 38-07104 Rev. *I

Page 3 of 16

[+] Feedback

Share Link: