CY22150FCT 데이터 시트보기 (PDF) - Cypress Semiconductor

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CY22150FCT

One-PLL General-Purpose Flash-Programmable and 2-Wire Serially Programmable Clock Generator

Cypress Semiconductor 

CY22150

Default Startup Condition for the CY22150

The default (programmed) condition of the device is generally set

by the distributor who programs the device using a customer

specific JEDEC file produced by CyClocksRT™. Parts shipped

from the factory are blank and unprogrammed. In this condition,

all bits are set to 0, all outputs are three-stated, and the crystal

oscillator circuit is active.

While you can develop your own subroutine to program any or

all of the individual registers described in the following pages, it

may be easier to use CyClocksRT to produce the required

register setting file.

The serial interface address of the CY22150 is 69H. If there is a

conflict with any other devices in your system, then this can also

be changed using CyClocksRT.

Frequency Calculations and Register Defini-

tions using the Serial Programming Interface

The CY22150 provides an industry standard serial interface for

volatile, in-system programming of unique frequencies and

options. Serial programming and reprogramming allows for quick

design changes and product enhancements, eliminates

inventory of old design parts, and simplifies manufacturing.

The Serial Programming Interface (SPI) provides volatile

programming. This means when the target system is powered

down, the CY22150 reverts to its pre-SPI state, as defined above

(programmed or unprogrammed). When the system is powered

back up again, the SPI registers must be reconfigured again.

All programmable registers in the CY22150 are addressed with

eight bits and contain eight bits of data. The CY22150 is a slave

device with an address of 1101001 (69H).

Table 2 lists the SPI registers and their definitions. Specific

register definitions and their allowable values are listed below.

Reference Frequency

The REF can be a crystal or a driven frequency. For crystals, the

frequency range must be between 8 MHz and 30 MHz. For a

driven frequency, the frequency range must be between 1 MHz

and 133 MHz.

Using a Crystal as the Reference Input

The input crystal oscillator of the CY22150 is an important

feature because of the flexibility it allows the user in selecting a

crystal as a REF source. The input oscillator has programmable

gain, allowing maximum compatibility with a reference crystal,

regardless of manufacturer, process, performance, and quality.

Programmable Crystal Input Oscillator Gain Settings

The Input crystal oscillator gain (XDRV) is controlled by two bits

in register 12H and are set according to Table 3 on page 5. The

parameters controlling the gain are the crystal frequency, the

internal crystal parasitic resistance (ESR, available from the

manufacturer), and the CapLoad setting during crystal startup.

Bits 3 and 4 of register 12H control the input crystal oscillator gain

setting. Bit 4 is the MSB of the setting, and bit 3 is the LSB. The

setting is programmed according to Table 3 on page 5. All other

bits in the register are reserved and should be programmed as

shown in Table 4 on page 5.

Using an External Clock as the Reference Input

The CY22150 also accepts an external clock as reference, with

speeds up to 133 MHz. With an external clock, the XDRV

(register 12H) bits must be set according to Table 5 on page 5.

Table 2. Summary Table – CY22150 Programmable Registers

Register

Description

D7

D6

D5

D4

D3

D2

D1

D0

09H CLKOE control

0

0

CLK6

CLK5 LCLK4 LCLK3 LCLK2 LCLK1

OCH DIV1SRC mux and

DIV1N divider

DIV1SRC DIV1N(6) DIV1N(5) DIV1N(4) DIV1N(3) DIV1N(2) DIV1N(1) DIV1N(0)

12H Input crystal oscillator

0

0

1

XDRV(1) XDRV(0)

0

0

0

drive control

13H Input load capacitor CapLoad CapLoad CapLoad CapLoad CapLoad CapLoad CapLoad CapLoad

control

(7)

(6)

(5)

(4)

(3)

(2)

(1)

(0)

40H Charge pump and PB

1

41H counter

PB(7)

1

PB(6)

0

PB(5)

Pump(2) Pump(1) Pump(0)

PB(4)

PB(3)

PB(2)

PB(9)

PB(1)

PB(8)

PB(0)

42H PO counter, Q counter PO

Q(6)

Q(5)

Q(4)

Q(3)

Q(2)

Q(1)

Q(0)

44H Crosspoint switch

matrix control

CLKSRC2 CLKSRC1 CLKSRC0 CLKSRC2 CLKSRC1 CLKSRC0 CLKSRC2 CLKSRC1

for LCLK1 for LCLK1 for LCLK1 for LCLK2 for LCLK2 for LCLK2 for LCLK3 for LCLK3

45H

CLKSRC0 CLKSRC2 CLKSRC1 CLKSRC0 CLKSRC2 CLKSRC1 CLKSRC0 CLKSRC2

for LCLK3 for LCLK4 for LCLK4 for LCLK4 for CLK5 for CLK5 for CLK5 for CLK6

46H

CLKSRC1 CLKSRC0

1

1

1

1

1

1

for CLK6 for CLK6

47H DIV2SRC mux and

DIV2N divider

DIV2SRC DIV2N(6) DIV2N(5) DIV2N(4) DIV2N(3) DIV2N(2) DIV2N(1) DIV2N(0)

Document #: 38-07104 Rev. *I

Page 4 of 16

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