CY22150FCT 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY22150FCT
Cypress Semiconductor
CY22150FCT Datasheet PDF : 16 Pages
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CY22150
Table 3. Programmable Crystal Input Oscillator Gain Settings
Crystal Input
Frequency
Cap Register Settings
Effective Load Capacitance
(CapLoad)
Crystal ESR
8 to 15 MHz
15 to 20 MHz
20 to 25 MHz
25 to 30 MHz
00H – 80H
6 pF to 12 pF
30Ω
60Ω
00
01
01
10
01
10
10
10
80H – C0H
12 pF to 18 pF
30Ω
60Ω
01
10
01
10
10
10
10
11
C0H – FFH
18 pF to 30 pF
30Ω
60Ω
01
10
10
10
10
11
11
N/A
Table 4. Bit Locations and Values
Address
D7
D6
D5
D4
D3
D2
D1
D0
12H
0
0
1
XDRV(1) XDRV(0)
0
0
0
Table 5. Programmable External Reference Input Oscillator Drive Settings
Reference Frequency
1 to 25 MHz
25 to 50 MHz
Drive Setting
00
01
50 to 90 MHz
10
90 to 133 MHz
11
Input Load Capacitors
Input load capacitors allow the user to set the load capacitance
of the CY22150 to match the input load capacitance from a
crystal. The value of the input load capacitors is determined by
8 bits in a programmable register [13H]. Total load capacitance
is determined by the formula:
CapLoad = (CL– CBRD – CCHIP)/0.09375 pF
where:
■ CL = specified load capacitance of your crystal.
■ CBRD = the total board capacitance, due to external capacitors
and board trace capacitance. In CyClocksRT, this value
defaults to 2 pF.
■ CCHIP = 6 pF.
■ 0.09375 pF = the step resolution available due to the 8-bit
register.
In CyclocksRT, only the crystal capacitance (CL) is specified.
CCHIP is set to 6 pF and CBRD defaults to 2 pF. If your board
capacitance is higher or lower than 2 pF, the formula given earlier
is used to calculate a new CapLoad value and programmed into
register 13H.
In CyClocksRT, enter the crystal capacitance (CL). The value of
CapLoad is determined automatically and programmed into the
CY22150. Through the SDAT and SCLK pins, the value can be
adjusted up or down if your board capacitance is greater or less
than 2 pF. For an external clock source, CapLoad defaults to 0.
See Table 6 on page 6 for CapLoad bit locations and values.
The input load capacitors are placed on the CY22150 die to
reduce external component cost. These capacitors are true
parallel-plate capacitors, designed to reduce the frequency shift
that occurs when nonlinear load capacitance is affected by load,
bias, supply, and temperature changes.
PLL Frequency, Q Counter [42H(6..0)]
The first counter is known as the Q counter. The Q counter
divides REF by its calculated value. Q is a 7 bit divider with a
maximum value of 127 and minimum value of 0. The primary
value of Q is determined by 7 bits in register 42H (6..0), but 2 is
added to this register value to achieve the total Q, or Qtotal. Qtotal
is defined by the formula:
Qtotal = Q + 2
The minimum value of Qtotal is 2. The maximum value of Qtotal is
129. Register 42H is defined in the table.
Stable operation of the CY22150 cannot be guaranteed if
REF/Qtotal falls below 250 kHz. Qtotal bit locations and values are
defined in Table 7 on page 6.
PLL Frequency, P Counter [40H(1..0)], [41H(7..0)],
[42H(7)
The next counter definition is the P (product) counter. The P
counter is multiplied with the (REF/Qtotal) value to achieve the
VCO frequency. The product counter, defined as Ptotal, is made
up of two internal variables, PB and PO. The formula for calcu-
lating Ptotal is:
Ptotal = (2(PB + 4) + PO)
PB is a 10-bit variable, defined by registers 40H(1:0) and
41H(7:0). The 2 LSBs of register 40H are the two MSBs of
variable PB. Bits 4..2 of register 40H are used to determine the
charge pump settings. The 3 MSBs of register 40H are preset
and reserved and cannot be changed. PO is a single bit variable,
defined in register 42H(7). This allows for odd numbers in Ptotal.
The remaining seven bits of 42H are used to define the Q
counter, as shown in Table 7.
The minimum value of Ptotal is 8. The maximum value of Ptotal is
2055. To achieve the minimum value of Ptotal, PB and PO should
both be programmed to 0. To achieve the maximum value of
Ptotal, PB should be programmed to 1023, and PO should be
programmed to 1.
Document #: 38-07104 Rev. *I
Page 5 of 16
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