CY22150FCT 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY22150FCT
Cypress Semiconductor
CY22150FCT Datasheet PDF : 16 Pages
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CY22150
Stable operation of the CY22150 cannot be guaranteed if the
value of (Ptotal*(REF/Qtotal)) is above 400 MHz or below
100 MHz. Registers 40H, 41H, and 42H are defined in Table 8.
PLL Post Divider Options [OCH(7..0)], [47H(7..0)]
The output of the VCO is routed through two independent
muxes, then to two divider banks to determine the final clock
output frequency. The mux determines if the clock signal feeding
into the divider banks is the calculated VCO frequency or REF.
There are two select muxes (DIV1SRC and DIV2SRC) and two
divider banks (Divider Bank 1 and Divider Bank 2) used to
determine this clock signal. The clock signal passing through
DIV1SRC and DIV2SRC is referred to as DIV1CLK and
DIV2CLK, respectively.
The divider banks have four unique divider options available: /2,
/3, /4, and /DIVxN. DIVxN is a variable that can be independently
programmed (DIV1N and DIV2N) for each of the two divider
banks. The minimum value of DIVxN is 4. The maximum value
of DIVxN is 127. A value of DIVxN below 4 is not guaranteed to
work properly.
DIV1SRC is a single bit variable, controlled by register OCH. The
remaining seven bits of register OCH determine the value of post
divider DIV1N.
DIV2SRC is a single bit variable, controlled by register 47H. The
remaining seven bits of register 47H determine the value of post
divider DIV2N.
Register OCH and 47H are defined in Table 9.
Charge Pump Settings [40H(2..0)]
The correct pump setting is important for PLL stability. Charge
pump settings are controlled by bits (4..2) of register 40H, and
are dependent on internal variable PB (see “PLL Frequency, P
Counter[40H(1..0)], [41H(7..0)], [42H(7)]”). Table 10 on page 6
summarizes the proper charge pump settings, based on Ptotal.
See Table 11 on page 7 for register 40H bit locations and values.
Table 6. Input Load Capacitor Register Bit Settings
Address
D7
D6
D5
D4
D3
D2
D1
D0
13H
CapLoad(7) CapLoad(6) CapLoad(5) CapLoad(4) CapLoad(3) CapLoad(2) CapLoad(1) CapLoad(0)
Table 7. P Counter Register Definition
Address
40H
41H
D7
1
PB(7)
D6
1
PB(6)
42H
PO
Q(6)
D5
0
PB(5)
Q(5)
D4
Pump(2)
PB(4)
Q(4)
D3
Pump(1)
PB(3)
Q(3)
D2
Pump(0)
PB(2)
Q(2)
D1
PB(9)
PB(1)
Q(1)
D0
PB(8)
PB(0)
Q(0)
Table 8. P Counter Register Definition
Address
40H
41H
D7
1
PB(7)
D6
1
PB(6)
42H
PO
Q(6)
D5
0
PB(5)
Q(5)
D4
Pump(2)
PB(4)
Q(4)
D3
Pump(1)
PB(3)
Q(3)
D2
Pump(0)
PB(2)
Q(2)
D1
PB(9)
PB(1)
Q(1)
D0
PB(8)
PB(0)
Q(0)
Table 9. PLL Post Divider Options
Address
OCH
47H
D7
DIV1SRC
DIV2SRC
D6
DIV1N(6)
DIV2N(6)
D5
DIV1N(5)
DIV2N(5)
D4
DIV1N(4)
DIV2N(4)
D3
DIV1N(3)
DIV2N(3)
D2
DIV1N(2)
DIV2N(2)
D1
DIV1N(1)
DIV2N(1)
D0
DIV1N(0)
DIV2N(0)
Table 10. Charge Pump Settings
Charge Pump Setting – Pump(2..0)
000
001
010
011
100
101, 110, 111
Calculated Ptotal
16 – 44
45 – 479
480 – 639
640 – 799
800 – 1023
Do not use – device will be unstable
Document #: 38-07104 Rev. *I
Page 6 of 16
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