CY22150FCT 데이터 시트보기 (PDF) - Cypress Semiconductor

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CY22150FCT

One-PLL General-Purpose Flash-Programmable and 2-Wire Serially Programmable Clock Generator

Cypress Semiconductor 

Figure 5. Start and Stop Frame

CY22150

SDAT

START

Transition

to next bit

STOP

SCLK

Figure 6. Frame Format (Device Address, R/W, Register Address, Register Data

SDAT

+

+

+

START DA6 DA5DA0 R/W ACK RA7 RA6RA1 RA0 ACK D7 D6 D1 D0

SCLK

+

+

+

ACK

STOP

Parameter

Description

Min

Max

Unit

fSCLK

Frequency of SCLK

400

kHz

Start mode time from SDA LOW to SCL LOW

0.6

μs

CLKLOW

CLKHIGH

tSU

tDH

SCLK LOW period

SCLK HIGH period

Data transition to SCLK HIGH

Data hold (SCLK LOW to data transition)

Rise time of SCLK and SDAT

1.3

μs

0.6

μs

100

ns

0

ns

300

ns

Fall time of SCLK and SDAT

300

ns

Stop mode time from SCLK HIGH to SDAT HIGH

0.6

μs

Stop mode to Start mode

1.3

μs

Document #: 38-07104 Rev. *I

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