CY22150FC 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY22150FC
Cypress Semiconductor
CY22150FC Datasheet PDF : 13 Pages
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CY22150
Table 6. P Counter Register Definition
Address
40H
41H
42H
D7
1
PB(7)
PO
D6
1
PB(6)
Q(6)
D5
0
PB(5)
Q(5)
D4
Pump(2)
PB(4)
Q(4)
D3
Pump(1)
PB(3)
Q(3)
D2
Pump(0)
PB(2)
Q(2)
D1
PB(9)
PB(1)
Q(1)
D0
PB(8)
PB(0)
Q(0)
Table 7. P Counter Register Definition
Address
40H
41H
42H
D7
1
PB(7)
PO
D6
1
PB(6)
Q(6)
D5
0
PB(5)
Q(5)
D4
Pump(2)
PB(4)
Q(4)
D3
Pump(1)
PB(3)
Q(3)
D2
Pump(0)
PB(2)
Q(2)
D1
PB(9)
PB(1)
Q(1)
D0
PB(8)
PB(0)
Q(0)
Table 8. PLL Post Divider Options
Address
OCH
47H
D7
DIV1SRC
DIV2SRC
D6
DIV1N(6)
DIV2N(6)
D5
DIV1N(5)
DIV2N(5)
D4
DIV1N(4)
DIV2N(4)
D3
DIV1N(3)
DIV2N(3)
D2
DIV1N(2)
DIV2N(2)
D1
DIV1N(1)
DIV2N(1)
D0
DIV1N(0)
DIV2N(0)
Table 9. Charge Pump Settings
Charge Pump Setting – Pump(2..0)
000
001
010
011
100
101, 110, 111
Calculated Ptotal
16 – 44
45 – 479
480 – 639
640 – 799
800 – 1023
Do not use – device will be unstable
Table 10. Register 40H Change Pump Bit Settings
Address
D7
D6
D5
40H
1
1
0
D4
Pump(2)
D3
Pump(1)
D2
Pump(0)
D1
PB(9)
D0
PB(8)
Although using the above table will guarantee stability, it is
recommended to use the Print Preview function in
CyClocksRT to determine the correct charge pump settings for
optimal jitter performance.
PLL stability cannot be guaranteed for values below 16 and
above 1023. If values above 1023 are needed, use
CyClocksRT to determine the best charge pump setting.
Clock Output Settings: CLKSRC – Clock Output Cross-
point Switch Matrix [44H(7..0)], [45H(7..0)], [46H(7..6)]
CLKOE – Clock Output Enable Control [09H(5..0)]
Every clock output can be defined to come from one of seven
unique frequency sources. The CLKSRC(2..0) crosspoint
switch matrix defines which source is attached to each
individual clock output. CLKSRC(2..0) is set in Registers 44H,
45H, and 46H. The remainder of register 46H(5:0) must be
written with the values stated in the register table when writing
register values 46H(7:6).
In addition, each clock output has individual CLKOE control,
set by register 09H(5..0).
When DIV1N is divisible by four, then CLKSRC(0,1,0) is
guaranteed to be rising edge phase-aligned with
CLKSRC(0,0,1). When DIV1N is six, then CLKSRC(0,1,1) is
guaranteed to be rising edge phase-aligned with
CLKSRC(0,0,1).
When DIV2N is divisible by four, then CLKSRC(1,0,1) is
guaranteed to be rising edge phase-aligned with
CLKSRC(1,0,0). When DIV2N is divisible by eight, then
CLKSRC(1,1,0) is guaranteed to be rising edge phase-aligned
with CLKSRC(1,0,0).
Each clock output has its own output enable, controlled by
register 09H(5..0). To enable an output, set the corresponding
CLKOE bit to 1. CLKOE settings are in Table 13.
The output swing of LCLK1 through LCLK4 is set by VDDL. The
output swing of CLK5 and CLK6 is set by VDD.
Test, Reserved, and Blank Registers
Writing to any of the following registers will cause the part to
exhibit abnormal behavior, as follows.
[00H to 08H]
[0AH to 0BH]
[0DH to 11H]
[14H to 3FH]
[43H]
[48H to FFH]
– Reserved
– Reserved
– Reserved
– Reserved
– Reserved
– Reserved.
Document #: 38-07104 Rev. *F
Page 6 of 13
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