CY62148VN 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY62148VN Datasheet PDF : 11 Pages
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Switching Characteristics
Over the Operating Range[5]
Parameter
Description
Read Cycle
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
OE LOW to Data Valid
OE LOW to Low Z[6]
OE HIGH to High Z[7]
CE LOW and to Low Z[6]
CE HIGH to High Z[6, 7]
tPU
CE1 LOW and CE2 HIGH to Power Up
tPD
CE1 HIGH and CE2 LOW to Power Down
Write Cycle[8, 9]
tWC
tSCE
tAW
tHA
tSA
tPWE
tSD
tHD
tHZWE
tLZWE
Write Cycle Time
CE1 LOW and CE2 HIGH to Write End
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
WE Pulse Width
Data Setup to Write End
Data Hold from Write End
WE LOW to High Z[6, 7]
WE HIGH to Low Z[6]
CY62148VN MoBL®
70 ns
Unit
Min
Max
70
ns
70
ns
10
ns
70
ns
35
ns
5
ns
25
ns
10
ns
25
ns
0
ns
70
ns
70
ns
60
ns
60
ns
0
ns
0
ns
50
ns
30
ns
0
ns
25
ns
10
ns
Notes
5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to VCC(typ.), and output loading of the specified
IOL/IOH and 30 pF load capacitance.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
7. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in (b) of AC Test Loads. Transition is measured ±200 mV from steady-state voltage.
8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
9. The minimum write cycle time for Write Cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 001-55636 Rev. **
Page 5 of 11
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