CY7B992-7JCT(2011) 데이터 시트보기 (PDF) - Cypress Semiconductor

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CY7B992-7JCT
(Rev.:2011)

Programmable Skew Clock Buffer

Cypress Semiconductor 

CY7B991

CY7B992

Capacitance

CMOS output buffer current and power dissipation specified at 50 MHz reference frequency.

Parameter

CIN

Description

Input Capacitance

Test Conditions

TA = 25 °C, f = 1 MHz, VCC = 5.0 V

Max

Unit

10

pF

Figure 3. AC Test Loads and Waveforms

5V

R1 R1=130

R2=91

CL = 50 pF (CL =30 pF for –2 and –5 devices)

CL

R2 (Includes fixture and probe capacitance)

TTL AC Test Load (CY7B991)

2.0V

Vth =1.5V

0.8V

0.0V

≤1ns

3.0V

2.0V

Vth =1.5V

0.8V

≤1ns

TTL Input Test Waveform (CY7B991)

VCC

R1=100

R1

R2=100

CL = 50 pF (CL =30 pF for –2 and –5 devices)

(Includes fixture and probe capacitance)

CL

R2

CMOS AC Test Load (CY7B992)

VCC

80%

Vth = VCC/2

20%

0.0V

≤3ns

80%

Vth = VCC/2

20%

≤3ns

CMOS Input Test Waveform (CY7B992)

Document Number: 38-07138 Rev. *I

Page 8 of 21

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