CY7C04312BV 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY7C04312BV Datasheet PDF : 37 Pages
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Switching Waveforms (continued)
Counter Reset [26, 31, 32, 33]
CLK
tCYC2
tCH2
tCL2
ADDRESS
INTERNAL
AX
ADDRESS
R/W
CNTLD
A0
tSW tHW
CY7C0430BV
CY7C04312BV
CY7C04314BV
tSA tHA
An
A1
An+1
An
An+1
tSCLD
tHCLD
CNTINC
tSCRST
CNTRST
DATAIN
tHCRST
tSD tHD
D0
DATAOUT
Q0
Counter
Reset
Write
Address 0
Read
Address 0
Read
Address 1
Notes:
32. CE0 = LB = UB = VIL; CE1 = MRST = MKLD = MKRD = CNTRD = VIH.
33. No dead cycle exists during counter reset. A Read or Write cycle may be coincidental with the counter reset.
Q1
Read
Address n
An+2
Qn
Document #: 38-06027 Rev. *A
Page 17 of 37
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