CY7C04312BV 데이터 시트보기 (PDF) - Cypress Semiconductor

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CY7C04312BV

10 Gb/s 3.3V QuadPort™ DSE Family

Cypress Semiconductor 

Switching Waveforms (continued)

Load and Read Address Counter[31, 34]

CLK

tSA

A0-A15

tCYC2

tCH2

tCL2

tHA

An

tSCLD

CNTLD

tHCLD

CNTINC

CNTRD

tSCINC

tHCINC

CY7C0430BV

CY7C04312BV

CY7C04314BV

Note 35

tCKLZ

Note 36

tCA2

tCKHZ

An+2[37]

tSCRD

tHCRD

INTERNAL

ADDRESS

DATAOUT

An

Qx–1

Qx

Load

External

Address

tCD2

An+1

tDC

Qn

Read Data with Counter

An+2

Qn+1

Notes:

34. CE0 = OE = LB = UB = VIL; CE1 = R/W = CNTRST = MRST = MKLD = MKRD = VIH.

35. Address in output mode. Host must not be driving address bus after time tCKLZ in next clock cycle.

36. Address in input mode. Host can drive address bus after tCKHZ.

37. This is the value of the address counter being read out on the address lines.

An+2

An+2

Qn+2

tCKHZ

Read

Internal

Address

tCKLZ

Qn+2

Document #: 38-06027 Rev. *A

Page 18 of 37

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