HM62V256 데이터 시트보기 (PDF) - Hitachi -> Renesas Electronics
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HM62V256 Datasheet PDF : 14 Pages
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HM62V256 Series
Write Cycle
HM62V256
-7
-8
-10
Parameter
Symbol Min Max Min Max Min Max Unit Notes
Write cycle time
tWC
70 — 85 — 100 — ns
Chip selection to end of write
tCW
50 — 75 — 80 — ns 4
Address setup time
tAS
0
—0
—0
— ns 5
Address valid to end of write
tAW
50 — 75 — 80 — ns
Write pulse width
tWP
45 — 55 — 60 — ns 3, 8
Write recovery time
tWR
0
—0
—0
— ns 6
Write to output in high-Z
tWHZ
0
25 0
30 0
35 ns 1, 2, 7
Data to write time overlap
tDW
30 — 35 — 40 — ns
Data hold from write time
tDH
0
—0
—0
— ns
Output active from end of write
tOW
10 — 10 — 10 — ns 2
Output disable to output in high-Z
tOHZ
0
25 0
30 0
35 ns 1, 2, 7
Notes: 1. tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit conditions and
are not referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. A write occurs during the overlap (tWP) of a low CS and a low WE. A write begins at the
later transition of CS going low or WE going low. A write ends at the earlier transition ofCS
going high or WE going high. tWP is measured from the beginning of write to the end of write.
4. tCW is measured from CS going low to the end of write.
5. tAS is measured from the address valid to the beginning of write.
6. tWR is measured from the earlier of WE or CS going high to the end of write cycle.
7. During this period, I/O pins are in the output state so that the input signals of the opposite phase
to the outputs must not be applied.
8. In the write cycle with OE low fixed, tWP must satisfy the following equation to avoid a problem of
data bus contention, tWP ≥ tWHZ max + tDW min.
9
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