CY7C1021CV26(2004) 데이터 시트보기 (PDF) - Cypress Semiconductor
부품명
상세내역
제조사
CY7C1021CV26 Datasheet PDF : 9 Pages
| |||
CY7C1021CV26
AC Test Loads and Waveforms[6]
2.6 V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
R1
1830Ω
R2
1976Ω
(a)
High-Z characteristics: 2.6V
OUTPUT
2.6V
GND
ALL INPUT PULSES
90%
90%
10%
10%
Rise Time: 1 V/ns
Fall Time: 1 V/ns
(b)
R 317Ω
5 pF
R2
351Ω
(c)
Switching Characteristics Over the Operating Range[7]
CY7C1021CV26-15
Parameter
Description
Min.
Max.
Unit
Read Cycle
tRC
tAA
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU[10]
tPD[10]
tDBE
tLZBE
tHZBE
Write Cycle[11]
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z[8]
OE HIGH to High-Z[8, 9]
CE LOW to Low-Z[8]
CE HIGH to High-Z[8, 9]
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable to Data Valid
Byte Enable to Low-Z
Byte Disable to High-Z
15
ns
15
ns
3
ns
15
ns
7
ns
0
ns
7
ns
3
ns
7
ns
0
ns
15
ns
7
ns
0
ns
7
ns
tWC
Write Cycle Time
15
ns
tSCE
CE LOW to Write End
10
ns
tAW
Address Set-Up to Write End
10
ns
tHA
Address Hold from Write End
0
ns
tSA
Address Set-Up to Write Start
0
ns
tPWE
WE Pulse Width
10
ns
tSD
Data Set-Up to Write End
8
ns
tHD
Data Hold from Write End
0
ns
Notes:
6. AC characteristics (except High-Z) are tested using the Thevenin load shown in Figure (a). High-Z characteristics are tested for all speeds using the test load
shown in Figure (c).
7. Test conditions assume signal transition time of 2.6 ns or less, timing reference levels of 1.3V, input pulse levels of 0 to 2.6V.
8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
9. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
10. This parameter is guaranteed by design and is not tested.
11. The internal Write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a Write,
and the transition of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write.
Document #: 38-05589 Rev. **
Page 4 of 9
Share Link: 