A386DX 데이터 시트보기 (PDF) - Intel
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A386DX Datasheet PDF : 139 Pages
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Intel386TM DX MICROPROCESSOR
GENERAL DATA AND ADDRESS REGISTERS
31
16 15
0
AX
EAX
BX
EBX
CX
ECX
DX
EDX
SI
ESI
DI
EDI
BP
EBP
SP
ESP
SEGMENT SELECTOR REGISTERS
15
0
CS
CODE
SS
STACK
DS
ES
FS
GS
INSTRUCTION POINTER
AND FLAGS REGISTER
31
16 15
0
DATA
*
IP
EIP
FLAGS EFLAGS
Figure 2-1 Intel386TM DX Base
Architecture Registers
The selectors are also task-specific so the segment
registers are automatically loaded with new context
upon a task switch operation
The other types of registers Control System Ad-
dress Debug and Test are primarily used by sys-
tem software
2 3 REGISTER DESCRIPTIONS
2 3 1 General Purpose Registers
General Purpose Registers The eight general pur-
pose registers of 32 bits hold data or address quanti-
ties The general registers Figure 2-2 support data
operands of 1 8 16 32 and 64 bits and bit fields of
1 to 32 bits They support address operands of 16
and 32 bits The 32-bit registers are named EAX
EBX ECX EDX ESI EDI EBP and ESP
The least significant 16 bits of the registers can be
accessed separately This is done by using the 16-
bit names of the registers AX BX CX DX SI DI
BP and SP When accessed as a 16-bit operand
the upper 16 bits of the register are neither used nor
changed
Finally 8-bit operations can individually access the
lowest byte (bits 0 – 7) and the higher byte (bits 8 –
15) of general purpose registers AX BX CX and DX
The lowest bytes are named AL BL CL and DL
respectively The higher bytes are named AH BH
CH and DH respectively The individual byte acces-
sibility offers additional flexibility for data operations
but is not used for effective address calculation
31
16 15 8 7 0
AH A X AL
EAX
BH B X BL
EBX
CH C X CL
ECX
DH D X DL
EDX
SI
ESI
DI
EDI
BP
EBP
SP
ESP
31
16 15
0
EIP
X
Y
IP
Figure 2-2 General Registers
and Instruction Pointer
2 3 2 Instruction Pointer
The instruction pointer Figure 2-2 is a 32-bit regis-
ter named EIP EIP holds the offset of the next in-
struction to be executed The offset is always rela-
tive to the base of the code segment (CS) The low-
er 16 bits (bits 0 – 15) of EIP contain the 16-bit in-
struction pointer named IP which is used by 16-bit
addressing
2 3 3 Flags Register
The Flags Register is a 32-bit register named
EFLAGS The defined bits and bit fields within
EFLAGS shown in Figure 2-3 control certain opera-
tions and indicate status of the Intel386 DX The
lower 16 bits (bit 0 – 15) of EFLAGS contain the
16-bit flag register named FLAGS which is most
useful when executing 8086 and 80286 code
9
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