ST40RA166 데이터 시트보기 (PDF) - STMicroelectronics
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ST40RA166 Datasheet PDF : 88 Pages
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ST40RA166
32-bit Embedded SuperH Device
PRELIMINARY DATA
JTAG
UDI
JTAG
Debug
SCIF
SCIF
Timer (TMU)
Real Time Clk
Interrupt Ctrl
Clock Ctrl
PLLs
Integer & FP
Execution Units
Registers
MMU
MMU
I Cache DCache
Cbus Bridge/
SuperHyway I/F
SuperHyway
PIO
Interface
5 Channel
DMA
Controller
EMI
PCI I/F 66MHz
ST40 Local Memory I/F
32 Data
PCI Peripherals
64 Data
SDRAM
24 Data
2 Channel
Control
32 Data
MPX
Coprocessor
Flash
Peripherals
Overview
The ST40RA166 is the first member of the ST40 family.
Based on the SH-4, SuperH CPU core from SuperH Inc, the
ST40RA166 is designed to work as a standalone device, or
as part of a two chip solution for application specific
systems.
Example applications the ST40RA166 is designed for
include digital consumer, embedded communications,
industrial and automotive. The high connectivity of the ST40
through its PCI bus and its dual memory uses makes it a
versatile device, ideal for data-intensive and high
performance applications.
System features
s 32-bit SuperH CPU
q 64-bit hardware FPU (1.16 GFLOPS)
q 128-bit vector unit for matrix manipulations
q 166 MHz, 300 MIPS (Dmips 1.1)
q Up to 664 Mbytes/s CPU bandwidth
q Direct mapped, on-chip, ICache (8 Kbytes) and DCache
(16 Kbytes)
s High-performance 5-channel DMA engine,
supporting 1D or 2D block moves and linked lists
s SuperHyway internal interconnect
q High throughput, low latency, split transaction packet
router
s Memory protection and VM system support
q 64-entry unified TLB, 4-entry instruction TLB
q 4 Gbytes address space
s Standard ST40 peripherals
q 2 synchronous serial ports with FIFO (SCIF)
q Timers and a real-time clock
IO devices
q Mailbox register for interprocessor communication
q Additional PIO
Bus interfaces
s Local memory interface SDRAM & DDR SDRAM
q Up to 100 MHz (1.6 Gbytes/sec peak throughput)
s PCI interface - 32-bit, 66/33 MHz, 3.3 V
s Enhanced memory interface (EMI)
q 32-bit bus, up to 83 MHz, for attaching peripherals
q High-speed, sync mode, burst flash ROM support
q SDRAM support
q MPX initiator and target interface
q Programmable MPX bus arbiter
March 2002
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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