80960CF-40(2002) 데이터 시트보기 (PDF) - Intel

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80960CF-40
(Rev.:2002)

32-Bit High-Performance Superscalar Embedded Microprocessor

Intel 

80960-40, -33, -25

Figure 41. Terminating a Burst with BTERM

PCLK

Quad-Word Write Request

NWAD = 0, NWDD = 0, NWDA = 0

Ready Enabled

ADS

A31:4, SUP,

DMA, INST,

D/C, BE3:0,

LOCK

W/R

Valid

BLAST

DT/R

DEN

READY

BTERM

A3:2

See Note

00

01

10

11

WAIT

D31:0

D0

D1

D2

D3

Note: READY adds memory access time to data transfers, whether or not the

bus access is a burst access. BTERM interrupts a bus access, whether or not

the bus access has more data transfers pending. Either the READY signal or

the BTERM signal may terminate a bus access when the signal is asserted during

the last (or only) data transfer of the bus access.

F_CX042A

Datasheet

63

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