CY7C1212F 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY7C1212F Datasheet PDF : 15 Pages
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CY7C1212F
Truth Table[2, 3, 4, 5, 6, 7]
Next Cycle
Unselected
Add. Used CE1 CE2 CE3 ZZ
None
HXX L
Unselected
None
LXH L
Unselected
None
LLX L
Unselected
None
LXH L
Unselected
None
LLX L
Begin Read
External
LHL
L
Begin Read
External
LHL
L
Continue Read Next
XXX L
Continue Read Next
XXX L
Continue Read Next
HXX L
Continue Read Next
HXX L
Suspend Read Current
XXX L
Suspend Read Current
XXX L
Suspend Read Current
HXX L
Suspend Read Current
HXX L
Begin Write
Current
XXX L
Begin Write
Current
HXX L
Begin Write
External
LHL
L
Continue Write Next
XXX L
Continue Write Next
HXX L
Suspend Write Current
XXX L
Suspend Write Current
HXX L
ZZ “Sleep”
None
XXX H
ADSP
X
L
L
H
H
L
H
H
H
X
X
H
H
X
X
H
X
H
H
X
H
X
X
ADSC
L
X
X
L
L
X
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
ADV
X
X
X
X
X
X
X
L
L
L
L
H
H
H
H
H
H
X
H
H
H
H
X
OE
DQ
Write
X Three-State X
X Three-State X
X Three-State X
X Three-State X
X Three-State X
X Three-State X
X Three-State Read
H Three-State Read
L DQ
Read
H Three-State Read
L DQ
Read
H Three-State Read
L DQ
Read
H Three-State Read
L DQ
Read
X Three-State Write
X Three-State Write
X Three-State Write
X Three-State Write
X Three-State Write
X Three-State Write
X Three-State Write
X Three-State X
Truth Table for Read/Write[2, 3]
Read
Function
GW
BWE
BWB
BWA
H
H
X
X
Read
H
L
H
H
Write Byte A – (DQA and DQPA)
Write Byte B – (DQB and DQPB)
Write All Bytes
H
L
H
L
H
L
L
H
H
L
L
L
Write All Bytes
L
X
X
X
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3.
WRITE =
GW = H.
L
when
any
one
or
more
Byte
Write
Enable
signals
(BWA,BWB)
and
BWE
=
L
or
GW
=
L.
WRITE
=
H
when
all
Byte
write
enable
signals
(BWA,
BWB),BWE,
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. CE1, CE2, and CE3 are available only in the TQFP package.
6. The SRAM always initiates a Read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A:B]. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to three-state. OE is
a don't care for the remainder of the Write cycle.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle all data bits are Three-State when
OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document #: 38-05423 Rev. *A
Page 6 of 15
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